参数资料
型号: MPC8378EVRAGD
厂商: Freescale Semiconductor
文件页数: 58/127页
文件大小: 0K
描述: MPU PWRQUICC II 400MHZ 689TEPBGA
标准包装: 27
系列: MPC83xx
处理器类型: 32-位 MPC83xx PowerQUICC II Pro
速度: 400MHz
电压: 1V
安装类型: 表面贴装
封装/外壳: 689-BBGA 裸露焊盘
供应商设备封装: 689-TEPBGA II(31x31)
包装: 托盘
配用: MPC8377E-RDBA-ND - BOARD REF DES MPC8377 REV 2.1
MPC8377E-MDS-PB-ND - BOARD MODULAR DEV SYSTEM
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
36
Freescale Semiconductor
10.2
Local Bus AC Electrical Specifications
This table describes the general timing parameters of the local bus interface of the device when in PLL
enable mode.
Table 38. Local Bus DC Electrical Characteristics (LBVDD =1.8 V)
At recommended operating conditions with LBVDD = 1.8 V.
Parameter
Conditions
Symbol
Min
Max
Unit
Supply voltage 1.8 V
LBVDD
1.71
1.89
V
Output high voltage
IOH = –1.0 mA
LBVDD = Min
VOH
LBVDD – 0.45
V
Output low voltage
IOL = 1.0 mA
LBVDD = Min
VOL
—0.45
V
Input high voltage
LBVDD = Min
VIH
0.65
× LBVDD
LBVDD + 0.3
V
Input low voltage
LBVDD = Min
VIL
–0.3
0.35
× LBVDD
V
Input high current
VIN
1 = LBV
DD
IIH
—10
μA
Input low current
VIN
1 = GND
IIL
–10
μA
Table 39. Local Bus General Timing Parameters—PLL Enable Mode
Parameter
Symbol1
Min
Max
Unit
Note
Local bus cycle time
tLBK
7.5
15
ns
Input setup to local bus clock (except LUPWAIT/LGTA)tLBIVKH
1.5
ns
Input hold from local bus clock
tLBIXKH
1.0
ns
LUPWAIT/LGTA input setup to local bus clock
tLBIVKH1
1.5
ns
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT1
1.5
ns
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT2
3—
ns
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT3
2.5
ns
Local bus clock to LALE rise
tLBKHLR
—4.5
ns
Local bus clock to output valid (except LALE)
tLBKHOV
—4.5
ns
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