参数资料
型号: MPC8379CVRALGA
厂商: Freescale Semiconductor
文件页数: 77/117页
文件大小: 0K
描述: MPU POWERQUICC II 667MHZ 689PBGA
标准包装: 27
系列: MPC83xx
处理器类型: 32-位 MPC83xx PowerQUICC II Pro
速度: 667MHz
电压: 1V
安装类型: 表面贴装
封装/外壳: 689-BBGA 裸露焊盘
供应商设备封装: 689-TEPBGA II(31x31)
包装: 托盘
MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
62
Freescale Semiconductor
This table provides the differential transmitter output AC characteristics for the SATA interface at Gen2i
or 3.0 Gbits/s transmission.
15.3
Differential Receiver (Rx) Input Characteristics
This section discusses the Gen1i/1.5G and Gen2i/3G differential receiver input AC characteristics.
15.3.1
Gen1i/1.5G Receiver Specifications
This table provides the Gen1i or 1.5 Gbits/s differential receiver input DC characteristics for the SATA
interface.
Table 55. Gen 2i/3G Transmitter AC Specifications
Parameter
Symbol
Min
Typical
Max
Units
Note
Channel speed
tCH_SPEED
—3.0
Gbps
Unit interval
TUI
333.2
333.33
335.11
ps
Total jitter
fC3dB=fBAUD/10
USATA_TXTJfB/10
——
0.3
UIp-p
Total jitter
fC3dB =fBAUD/500
USATA_TXTJfB/500
0.37
UIp-p
Total jitter
fC3dB =fBAUD/1667
USATA_TXTJfB/1667
0.55
UIp-p
Deterministic jitter
fC3dB =fBAUD/10
USATA_TXDJfB/10
0.17
UIp-p
Deterministic jitter
fC3dB =fBAUD/500
USATA_TXDJfB/500
0.19
UIp-p
Deterministic jitter
fC3dB =fBAUD/1667
USATA_TXDJfB/1667
0.35
UIp-p
Note:
1. Measured at Tx output pins peak to peak phase variation, random data pattern.
Table 56. Gen1i/1.5G Receiver Input DC Specifications
Parameter
Symbol
Min
Typical
Max
Units
Note
Differential input voltage
VSATA_RXDIFF
240
500
600
mVp-p
Differential Rx input impedance
ZSATA_RXSEIM
85
100
115
Ω
Note:
1. Voltage relative to common of either signal comprising a differential pair.
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