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参数资料
型号： MPC8379EVRANGA
厂商： FREESCALE SEMICONDUCTOR INC
元件分类： 微控制器/微处理器
英文描述： 32-BIT, 400 MHz, MICROPROCESSOR, PBGA689
封装： 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689
文件页数： 17/114页
文件大小： 1337K
代理商： MPC8379EVRANGA
MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
113
Document Revision History
26 Document Revision History
Table 83 provides a revision history for this hardware specification.
Table 83. Document Revision History
Revision
Date
Substantive Change(s)
2
10/2009
In Table 3, “Recommended Operating Conditions,” added “Operating temperature range” values.
In Table 5, “MPC8377E Power Dissipation 1,” corrected maximal application for 800/400 MHz to 4.3 W.
In Table 5, “MPC8377E Power Dissipation 1,” added a column for “Typical Application at Tj =65°C (W)”.
In Table 5, “MPC8377E Power Dissipation 1,” added a column for “Sleep Power at Tj =65°C (W)”.
In Table 10, removed overbar from CFG_CLKIN_DIV.
In Table 16, “Current Draw Characteristics for MVREF,” updated IMVREF maximum value for both DDR1
and DDR2 to 600 and 400
μA, respectively. Also, updated Note 1 and added Note 2.
In Table 19, “DDR1 and DDR2 SDRAM Input AC Timing Specifications,” column headings renamed to
“Min” and “Max”. Footnote 2 updated to state “T is the MCK clock period”.
In Table 19, “DDR1 and DDR2 SDRAM Input AC Timing Specifications,” and Table 20, “DDR1 and
DDR2 SDRAM Output AC Timing Specifications,” clarified that the frequency parameters are data rates.
In Table 28, “RMII Transmit AC Timing Specifications,” updated tRMTDXI to 2.0 ns.
In Table 56, Gen 1i/1.5G Receiver AC Specifications,” and Table 58, Gen 2i/3G Receiver AC
Specifications,” corrected titles from “Transmitter” to “Receiver”.
In Table 68, “TePBGA II Pinout Listing,” removed pin THERM0; it is now Reserved. Also added 1.05 V
to VDD pin.
In Table 70, “Operating Frequencies for TePBGA II,” corrected “DDR2 memory bus frequency (MCK)”
range to 125–200.
In Table 75, “e300 Core PLL Configuration,” added 3.5:1 and 4:1 core_clk: csb_clk ratio options.
In Table 76, “Example Clock Frequency Combinations,” updated column heading to “DDR data rate” .
In Section 19.2, “SPI AC Timing Specifications,” corrected tNIKHOX and tNEKHOX to tNIKHOV and tNEKHOV,
respectively.
1
02/2009
In Table 3, “Recommended Operating Conditions,” added two new rows for 800 MHz, and created two
rows for SerDes. In addition, changed 666 to 667 MHz.
In Table 5, “MPC8377E Power Dissipation 1,” added Notes 4 and 5. In addition, changed 666 to 667
MHz.
In Table 12, “DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V,” Table 20, “DDR1 and
DDR2 SDRAM Output AC Timing Specifications,” and Table 68, “TePBGA II Pinout Listing,” added
footnote to references to MVREF, MDQ, and MDQS, referencing AN3665,
MPC837xE Design Checklist.
In Table 20, updated tDDKHCX minimum value for 333 MHz to 2.40.
In Table 68, “TePBGA II Pinout Listing,” added footnote to USBDR_STP_SUSPEND and modified
footnote 10 and added footnote 13.
In Table 70, “Operating Frequencies for TePBGA II,” changed 667 to 800 MHz for
core_clk.
In Table 76, “Example Clock Frequency Combinations,” added 800 MHz cells for e300 core.
Updated part numbering information in AF column in Table 80, “Part Numbering Nomenclature.” In
addition, modified extended temperature information in notes 1 and 4.
In Table 81, “Available Parts (Core/DDR Data Rate),” added new row for 800/400 MHz.
0
12/2008 Initial public release.
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