参数资料
型号: MPC8379VRAJFA
厂商: Freescale Semiconductor
文件页数: 75/117页
文件大小: 0K
描述: MPU POWERQUICC II 533MHZ 689PBGA
标准包装: 27
系列: MPC83xx
处理器类型: 32-位 MPC83xx PowerQUICC II Pro
速度: 533MHz
电压: 1V
安装类型: 表面贴装
封装/外壳: 689-BBGA 裸露焊盘
供应商设备封装: 689-TEPBGA II(31x31)
包装: 托盘
MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
60
Freescale Semiconductor
15.1
Requirements for SATA REF_CLK
The reference clock is a single ended input clock required for the SATA interface operation. The AC
requirements for the SATA reference clock are listed in the Table 51.
This figure shows the SATA reference clock timing waveform.
Figure 42. SATA Reference Clock Timing Waveform
15.2
Transmitter (Tx) Output Characteristics
This section discusses the Gen1i/1.5G and Gen2i/3G transmitter output characteristics for the SATA
interface.
Table 51. SATA Reference Clock Input Requirements
Parameter
Condition
Symbol
Min
Typical
Max
Unit
Note
SD_REF_CLK/ SD_REF_CLK
frequency range
—tCLK_REF
100/125/150
MHz
SD_REF_CLK/ SD_REF_CLK
clock frequency tolerance
—tCLK_TOL
–350
0
+350
ppm
SD_REF_CLK/ SD_REF_CLK
reference clock duty cycle
Measured at 1.6V
tCLK_DUTY
40
50
60
%
SD_REF_CLK/ SD_REF_CLK
cycle to cycle Clock jitter (period
jitter)
Cycle-to-cycle at
ref clock input
tCLK_CJ
100
ps
SD_REF_CLK/ SD_REF_CLK total
reference clock jitter, phase jitter
(peak-peak)
Peak-to-peak jitter
at ref clock input
tCLK_PJ
–50
+50
ps
Notes:
1. Only 100/125/150 MHz have been tested, other in between values will not work correctly with the rest of the system.
2. In a frequency band from 150 kHz to 15 MHz at BER of 10-12.
3. Total peak to peak Deterministic Jitter "DJ" should be less than or equal to 50 ps.
TH
TL
Ref_CLK
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