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| 型号： | MPC852TVR100 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 100 MHz, RISC PROCESSOR, PBGA256 |
| 封装： | PLASTIC, BGA-256 |
| 文件页数： | 4/80页 |
| 文件大小： | 2070K |
| 代理商： | MPC852TVR100 |
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MPC852T Hardware Specifications, Rev. 3.1
12
Freescale Semiconductor
Layout Practices
The MBMR[GPLB4DIS], PAPAR, PADIR, PBPAR, PBDIR, PCPAR, and PCDIR should be configured with the
mandatory value in Table 6 in the boot code after the reset deasserts.
11 Layout Practices
Each VDD pin on the MPC852T should be provided with a low-impedance path to the board’s supply. Each GND
pin should likewise be provided with a low-impedance path to ground. The power supply pins drive distinct groups
of logic on chip. The VDD power supply should be bypassed to ground using at least four 0.1 F by-pass capacitors
located as close as possible to the four sides of the package. Each board designed should be characterized and
additional appropriate decoupling capacitors should be used if required. The capacitor leads and associated printed
circuit traces connecting to chip VDD and GND should be kept to less than half an inch per capacitor lead. At a
minimum, a four-layer board employing two inner layers as VDD and GND planes should be used.
All output pins on the MPC852T have fast rise and fall times. Printed circuit (PC) trace interconnection length
should be minimized to minimize undershoot and reflections that these fast output switching times cause. This
recommendation particularly applies to the address and data buses. Maximum PC trace lengths of six inches are
recommended. Capacitance calculations should consider all device loads as well as parasitic capacitances that the
PC traces cause. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher
capacitive loads, because these loads create higher transient currents in the VDD and GND circuits. Pull up all unused
inputs or signals that are inputs during reset. Special care should be taken to minimize the noise levels on the PLL
Table 6. Mandatory Reset Configuration of MPC852T
Register/Configuration
Field
Value
(binary)
HRCW
(Hardware reset configuration word)
HRCW[DBGC]
X1
SIUMCR
(SIU module configuration register)
SIUMCR[DBGC]
X1
MBMR
(Machine B mode register)
MBMR[GPLB4DIS}
0
PAPAR
(Port A pin assignment register)
PAPAR[4-7]
PAPAR[12-15]
0
PADIR
(Port A Data Direction Register)
PADIR[4-7]
PADIR[12-15]
1
PBPAR
(Port B Pin Assignment Register)
PBPAR[14]
PBPAR[16-23]
PBPAR[26-27]
0
PBDIR
(Port B Data Direction Register)
PBDIR[14]
PBDIR[16-23]
PBDIR[26-27]
1
PCPAR
(Port C Pin Assignment Register)
PCPAR[8-11]
PCDIR[14]
0
PCDIR
(Port C Data Direction Register)
PCDIR[8-11]
PCDIR[14]
1
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC852TVR100A | 功能描述:微处理器 - MPU Ethernet 100 MHz RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC852TVR100A | 制造商:Freescale Semiconductor 功能描述:IC COMMUNICATIONS CONTROLLER CMOS BGA |
| MPC852TVR50 | 制造商:Freescale Semiconductor 功能描述: |
| MPC852TVR50A | 功能描述:微处理器 - MPU Ethernet 50 MHz RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC852TVR66 | 功能描述:IC MPU POWERQUICC 66MHZ 256-PBGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微处理器 系列:MPC8xx 标准包装:2 系列:MPC8xx 处理器类型:32-位 MPC8xx PowerQUICC 特点:- 速度:133MHz 电压:3.3V 安装类型:表面贴装 封装/外壳:357-BBGA 供应商设备封装:357-PBGA（25x25） 包装:托盘 |
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