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参数资料
型号： MPC8533VTAQJB
厂商： FREESCALE SEMICONDUCTOR INC
元件分类： 微控制器/微处理器
英文描述： 32-BIT, 1000 MHz, RISC PROCESSOR, PBGA783
封装： 29 X 29 MM, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-783
文件页数： 83/116页
文件大小： 1277K
代理商： MPC8533VTAQJB
MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
69
PCI Express
The other detailed AC requirements of the SerDes reference clocks is defined by each interface protocol
based on application usage. Refer to the following sections for detailed information:
Section 17.2, “AC Requirements for PCI Express SerDes Clocks”
16.2.4.1
Spread Spectrum Clock
SD1_REF_CLK/SD1_REF_CLK were designed to work with a spread spectrum clock (+0 to –0.5%
spreading at 30–33 kHz rate is allowed), assuming both ends have same reference clock. For better results,
a source without significant unintended modulation should be used.
SD2_REF_CLK/SD2_REF_CLK are not intended to be used with, and should not be clocked by, a spread
spectrum clock source.
16.3
SerDes Transmitter and Receiver Reference Circuits
Figure 51 shows the reference circuits for SerDes data lane’s transmitter and receiver.
Figure 51. SerDes Transmitter and Receiver Reference Circuits
The DC and AC specification of SerDes data lanes are defined in section below (PCI Express) in this
document based on the application usage:
Section 17, “PCI Express”
Please note that external AC Coupling capacitor is required for the above serial transmission protocols
with the capacitor value defined in specification of each protocol section.
17 PCI Express
This section describes the DC and AC electrical specifications for the PCI Express bus of the MPC8533E.
17.1
DC Requirements for PCI Express SD_REF_CLK and
SD_REF_CLK
For more information, see Section 16.2, “SerDes Reference Clocks.”
50
Ω
Receiver
Transmitter
50
Ω
50
Ω
SD1_TX
n or
SD2_TX
n
SD1_RX
n or
SD2_RX
n
50
Ω
SD1_TX
n or
SD2_TX
n
SD1_RX
n or
SD2_RX
n
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