- 您现在的位置：买卖IC网 > PDF目录45366 > MPC8535EBVTANGA (FREESCALE SEMICONDUCTOR INC) 32-BIT, 800 MHz, MICROPROCESSOR, PBGA783 PDF资料下载
参数资料
| 型号： | MPC8535EBVTANGA |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 800 MHz, MICROPROCESSOR, PBGA783 |
| 封装： | 29 X 29 MM, 2.80 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, FCBGA-783 |
| 文件页数： | 40/126页 |
| 文件大小： | 2861K |
| 代理商： | MPC8535EBVTANGA |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页当前第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3
Pin Map
Freescale Semiconductor
20
Notes:
1. All multiplexed signals may be listed only once and may not re-occur.
2. Recommend a weak pull-up resistor (2–10 K
Ω) be placed on this pin to OVDD.
3. This pin must always be pulled-high.
4. This pin is an open drain signal.
5. This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the processor is in the
reset state. This pull-up is designed such that it can be overpowered by an external 4.7-k
Ω pull-down resistor. However, if
the signal is intended to be high after reset, and if there is any device on the net which might pull down the value of the net
at reset, then a pullup or active driver is needed.
6. Treat these pins as no connects (NC) unless using debug address functionality.
7. The value of LA[28:31] during reset sets the CCB clock to SYSCLK PLL ratio. These pins require 4.7-k
Ω pull-up or pull-down
resistors. See Section 22.2, “CCB/SYSCLK PLL Ratio.”
8. The value of LALE, LGPL2 and LBCTL at reset set the e500 core clock to CCB Clock PLL ratio. These pins require 4.7-k
Ω
pull-up or pull-down resistors. See the Section 22.3, “e500 Core PLL Ratio.”
9. Functionally, this pin is an output, but structurally it is an I/O because it either samples configuration input during reset or
because it has other manufacturing test functions. This pin will therefore be described as an I/O for boundary scan.
10.For proper state of these signals during reset, UART_SOUT[1] must be pulled down to GND through a resistor.
UART_SOUT[0] can be pulled up or left without a resistor. However, if there is any device on the net which might pull down
the value of the net at reset, then a pullup is needed on UART_SOUT[0].
11.This output is actively driven during reset rather than being three-stated during reset.
12.These JTAG pins have weak internal pull-up P-FETs that are always enabled.
13.These pins are connected to the VDD_CORE/VDD_PLAT/GND planes internally and may be used by the core power supply to
improve tracking and regulation.
15. These pins have other manufacturing or debug test functions. It’s recommended to add both pull-up resistor pads to OVDD
and pull-down resistor pads to GND on board to support future debug testing when needed.
16. If this pin is connected to a device that pulls down during reset, an external pull-up is required to drive this pin to a safe
state during reset.
17. This pin is only an output in FIFO mode when used as Rx Flow Control.
18. Do not connect.
19.These must be pulled up (100
Ω- 1 kΩ) to OVDD.
20. Independent supplies derived from board VDD.
21. Recommend a pull-up resistor (1 K
Ω) be placed on this pin to OVDD.
22. The following pins must NOT be pulled down during power-on reset: MDVAL, UART_SOUT[0], EC_MDC, TSEC1_TXD[3],
TSEC3_TXD[7], HRESET_REQ, TRIG_OUT/READY/QUIESCE, MSRCID[2:4], ASLEEP.
23. This pin requires an external 4.7-k
Ω pull-down resistor to prevent PHY from seeing a valid Transmit Enable before it is
actively driven.
24. General-Purpose POR configuration of user system.
Table 1. MPC8535E Pinout Listing
Signal
Signal Name
Package Pin Number
Pin Type
Power
Supply
Notes
相关PDF资料 |
PDF描述 |
|---|---|
| MPC8535BVTAQG | 32-BIT, 1000 MHz, MICROPROCESSOR, PBGA783 |
| MPC8535CVTATH | 32-BIT, 1250 MHz, MICROPROCESSOR, PBGA783 |
| MPC8535AVTANG | 32-BIT, 800 MHz, MICROPROCESSOR, PBGA783 |
| MPC8535EBVTAKGA | 32-BIT, 600 MHz, MICROPROCESSOR, PBGA783 |
| MPC8535CVTANGA | 32-BIT, 800 MHz, MICROPROCESSOR, PBGA783 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC8535EBVTAQG | 功能描述:微处理器 - MPU 8535E INDUSTRIAL 1000 RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8535EBVTAQGA | 功能描述:微处理器 - MPU 8535 Encrypted RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8535EBVTATH | 功能描述:微处理器 - MPU 8535E INDUSTRIAL 1250 RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8535EBVTATHA | 功能描述:微处理器 - MPU 8535 Encrypted RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8535EBVTATLA | 功能描述:微处理器 - MPU 8535 ENCRYPTED RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
发布紧急采购，3分钟左右您将得到回复。