参数资料
型号: MPC8535ECVTATH
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 1250 MHz, MICROPROCESSOR, PBGA783
封装: 29 X 29 MM, 2.80 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, FCBGA-783
文件页数: 63/126页
文件大小: 2861K
代理商: MPC8535ECVTATH
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
41
2.9.2
FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing Specifications
The AC timing specifications for FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI are presented in this section.
2.9.2.1
FIFO AC Specifications
The basis for the AC specifications for the eTSEC’s FIFO modes is the double data rate RGMII and RTBI specifications, since
they have similar performance and are described in a source-synchronous fashion like FIFO modes. However, the FIFO
interface provides deliberate skew between the transmitted data and source clock in GMII fashion.
When the eTSEC is configured for FIFO modes, all clocks are supplied from external sources to the relevant eTSEC interface.
That is, the transmit clock must be applied to the eTSECn’s TSECn_TX_CLK, while the receive clock must be applied to pin
TSECn_RX_CLK. The eTSEC internally uses the transmit clock to synchronously generate transmit data and outputs an echoed
copy of the transmit clock back out onto the TSECn_GTX_CLK pin (while transmit data appears on TSECn_TXD[7:0], for
example). It is intended that external receivers capture eTSEC transmit data using the clock on TSECn_GTX_CLK as a source-
synchronous timing reference. Typically, the clock edge that launched the data can be used, since the clock is delayed by the
eTSEC to allow acceptable set-up margin at the receiver. Note that there is relationship between the maximum FIFO speed and
the platform speed. For more information see Section 2.4.6, “Platform to FIFO Restrictions.”
A summary of the FIFO AC specifications appears in Table 26 and Table 27.
Table 25. RGMII, RTBI, and FIFO DC Electrical Characteristics
Parameters
Symbol
Min
Max
Unit
Notes
Supply voltage 2.5 V
LVDD/TVDD
2.37
2.63
V
1,2
1 LV
DD supports eTSECs 1.
2 TV
DD supports eTSECs 3.
Output high voltage
(LVDD/TVDD = Min, IOH = –1.0 mA)
VOH
2.00
LVDD/TVDD + 0.3
V
Output low voltage
(LVDD/TVDD = Min, IOL = 1.0 mA)
VOL
GND – 0.3
0.40
V
Input high voltage
VIH
1.70
LVDD/TVDD + 0.3
V
Input low voltage
VIL
–0.3
0.70
V
Input high current
(VIN = LVDD, VIN = TVDD)
IIH
—10
μA
1, 2,3
3 Note that the symbol V
IN, in this case, represents the LVIN and TVIN symbols referenced in Table 1 and Table 2.
Input low current
(VIN = GND)
IIL
–15
μA
3
Note:
Table 26. FIFO Mode Transmit AC Timing Specification
Parameter/Condition
Symbol
Min
Typ
Max
Unit
TX_CLK, GTX_CLK clock period2
tFIT
6.0
8.0
100
ns
TX_CLK, GTX_CLK duty cycle
tFITH
45
50
55
%
TX_CLK, GTX_CLK peak-to-peak jitter
tFITJ
250
ps
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