参数资料
型号: MPC8536AVTANGA
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 800 MHz, MICROPROCESSOR, PBGA783
封装: 29 X 29 MM, 2.80 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, FCBGA-783
文件页数: 127/127页
文件大小: 1893K
代理商: MPC8536AVTANGA
High-Speed Serial Interfaces
MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
99
Figure 67. Single-Ended Measurement Points for Rise and Fall Time Matching
The other detailed AC requirements of the SerDes Reference Clocks is defined by each interface protocol based on application
usage. See the following sections for detailed information:
2.20.2.4.1
Spread Spectrum Clock
SD1_REF_CLK/SD1_REF_CLK were designed to work with a spread spectrum clock (+0 to -0.5% spreading at 30–33 kHz
rate is allowed), assuming both ends have same reference clock. For better results, a source without significant unintended
modulation should be used.
SD2_REF_CLK/SD2_REF_CLK are not intended to be used with, and should not be clocked by, a spread spectrum clock
source.
2.20.3
SerDes Transmitter and Receiver Reference Circuits
Figure 68 shows the reference circuits for SerDes data lane’s transmitter and receiver.
Figure 68. SerDes Transmitter and Receiver Reference Circuits
The DC and AC specification of SerDes data lanes are defined in each interface protocol section below (PCI Express, SATA or
SGMII) in this document based on the application usage:
Please note that external AC Coupling capacitor is required for the above three serial transmission protocols with the capacitor
value defined in specification of each protocol section.
50
Ω
50
Ω
Receiver
Transmitter
SD1_TXn or
SD2_TXn
SD1_TXn or
SD2_TXn
SD1_RXn or
SD2_RXn
SD1_RXn or
SD2_RXn
50
Ω
50
Ω
相关PDF资料
PDF描述
MPC8536ECVTAKG 32-BIT, 600 MHz, MICROPROCESSOR, PBGA783
MPC8536ECVTATH 32-BIT, 1250 MHz, MICROPROCESSOR, PBGA783
MPC853TVR50 32-BIT, 50 MHz, RISC PROCESSOR, PBGA256
MPC853TVR80 32-BIT, 80 MHz, RISC PROCESSOR, PBGA256
MPC8540CPX833LB 32-BIT, 667 MHz, MICROPROCESSOR, PBGA783
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