参数资料
型号: MPC8536EAVTAKGA
厂商: Freescale Semiconductor
文件页数: 52/126页
文件大小: 0K
描述: MPU POWERQUICC III 783FCPBGA
标准包装: 1
系列: MPC85xx
处理器类型: 32-位 MPC85xx PowerQUICC III
速度: 600MHz
电压: 1V
安装类型: 表面贴装
封装/外壳: 783-BBGA,FCBGA
供应商设备封装: 783-FCPBGA(29x29)
包装: 托盘
Electrical Characteristics
MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
31
2.4.6
Platform to FIFO Restrictions
Please note the following FIFO maximum speed restrictions based on platform speed. The “platform clock (CCB) frequency”
in the following formula refers to the maximum platform (CCB) frequency of the speed bins the part belongs to, which is
defined in Table 73.
For FIFO GMII mode:
FIFO TX/RX clock frequency <= platform clock frequency/3.2
For example, if the platform frequency is 533 MHz, the FIFO TX/RX clock frequency should be no more than 167 MHz
For FIFO encoded mode:
FIFO TX/RX clock frequency <= platform clock frequency/3.2
For example, if the platform frequency is 533 MHz, the FIFO TX/RX clock frequency should be no more than
167 MHz
2.4.7
Other Input Clocks
For information on the input clocks of other functional blocks of the platform such as SerDes, and eTSEC, see the specific
section of this document.
2.5
RESET Initialization
This section describes the AC electrical specifications for the RESET initialization timing requirements of the chip. This table
provides the RESET initialization AC timing specifications for the DDR SDRAM component(s).
This table provides the PLL lock times.
Table 10. RESET Initialization Timing Specifications
Parameter/Condition
Min
Max
Unit
Notes
Required assertion time of HREST
100
μs—
Minimum assertion time for SRESET
3—
Sysclk
1
PLL input setup time with stable SYSCLK before HRESET negation
100
μs—
Input setup time for POR configurations (other than PLL config) with respect to negation of
HRESET
4
SYSCLKs
1
Input hold time for all POR configurations (including PLL config) with respect to negation of
HRESET
2
SYSCLKs
1
Maximum valid-to-high impedance time for actively driven POR configurations with respect to
negation of HRESET
5
SYSCLKs
1
HRESET rise time
1
SYSCLK
Notes:
1. SYSCLK is the primary clock input for the chip.
Table 11. PLL Lock Times
Parameter/Condition
Min
Max
Unit
Notes
PLL lock times
100
μs—
Local bus PLL
50
μs—
PCI bus lock time
50
μs—
相关PDF资料
PDF描述
FSM44DSEF-S13 CONN EDGECARD 88POS .156 EXTEND
AMM43DTAI-S189 CONN EDGECARD 86POS R/A .156 SLD
AMM43DTMI-S189 CONN EDGECARD 86POS R/A .156 SLD
AMM43DTBI-S189 CONN EDGECARD 86POS R/A .156 SLD
AMC50DRYI-S93 CONN EDGECARD 100PS DIP .100 SLD
相关代理商/技术参数
参数描述
MPC8536EAVTANG 功能描述:微处理器 - MPU PQ38S 8536 SQUID RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324
MPC8536EAVTANGA 功能描述:微处理器 - MPU 8536 Encrypted RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324
MPC8536EAVTAQG 功能描述:微处理器 - MPU PQ38S 8536 SQUID RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324
MPC8536EAVTAQGA 功能描述:微处理器 - MPU 8536 Encrypted RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324
MPC8536EAVTATGA 功能描述:微处理器 - MPU 8536 Encrypted RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324