参数资料
型号: MPC8536ECVTAQGA
厂商: Freescale Semiconductor
文件页数: 114/126页
文件大小: 0K
描述: MPU PWRQUICC III 1000MHZ 783PBGA
产品培训模块: MPC8536E QUICC III Processor
标准包装: 1
系列: MPC85xx
处理器类型: 32-位 MPC85xx PowerQUICC III
速度: 1.0GHz
电压: 1V
安装类型: 表面贴装
封装/外壳: 783-BBGA,FCBGA
供应商设备封装: 783-FCPBGA(29x29)
包装: 托盘
其它名称: MPC8536ECVTAQG
MPC8536ECVTAQG-ND
MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Electrical Characteristics
Freescale Semiconductor
88
2.18
GPIO
This section describes the DC and AC electrical specifications for the GPIO interface of the chip.
2.18.1
GPIO DC Electrical Characteristics
This table provides the DC electrical characteristics for the GPIO interface.
2.18.2
GPIO AC Electrical Specifications
This table provides the GPIO input and output AC timing specifications.
This figure provides the AC test load for the GPIO.
Figure 53. GPIO AC Test Load
Table 65. GPIO DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
High-level input voltage
VIH
2OVDD + 0.3
V
Low-level input voltage
VIL
– 0.3
0.8
V
Input current
(VIN
1 = 0 V or V
IN = VDD)
IIN
—±5
μA
High-level output voltage
(OVDD = min, IOH = –2 mA)
VOH
2.4
V
Low-level output voltage
(OVDD = min, IOL = 2 mA)
VOL
—0.4
V
Note:
1. The symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.
Table 66. GPIO Input and Output AC Timing Specifications1
Characteristic
Symbol 2
Min
Unit
Notes
GPIO inputs—minimum pulse width
tPIWID
7.5
ns
3
GPIO outputs—minimum pulse width
tGTOWID
12
ns
Notes:
1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings
are measured at the pin.
2. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any
external synchronous logic. GPIO inputs are required to be valid for at least tPIWID ns to ensure proper operation.
3. The minimum pulse width is a function of the MPX/Platform clock. The minimum pulse width must be greater than or equal
to 4 times the MPX/Platform clock period.
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
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