参数资料
型号: MPC8544EAVTANG
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 400 MHz, MICROPROCESSOR, PBGA783
封装: 29 X 29 MM, 1 MM PITCH, LEAD FREE, PLASTIC, FC-PBGA-783
文件页数: 128/128页
文件大小: 1411K
代理商: MPC8544EAVTANG
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
99
Clocking
19 Clocking
This section describes the PLL configuration of the MPC8544E. Note that the platform clock is identical
to the core complex bus (CCB) clock.
19.1
Clock Ranges
Table 64 provides the clocking specifications for the processor cores and Table 65 provides the clocking
specifications for the memory bus.
24. When a PCI block is disabled, either the POR config pin that selects between internal and external arbiter must be pulled
down to select external arbiter if there is any other PCI device connected on the PCI bus, or leave the address pins as No
Connect or terminated through 2–10 k
Ω pull-up resistors with the default of internal arbiter if the address pins are not
connected to any other PCI device. The PCI block will drive the address pins if it is configured to be the PCI arbiter—through
POR config pins—irrespective of whether it is disabled via the DEVDISR register or not. It may cause contention if there is
any other PCI device connected on the bus.
25. MDIC0 is grounded through an 18.2-
Ω precision 1% resistor and MDIC1 is connected GVDD through an 18.2-Ω precision
1% resistor. These pins are used for automatic calibration of the DDR IOs.
26. For SGMII mode.
27. Connect to GND.
Table 64. Processor Core Clocking Specifications
Characteristic
Maximum Processor Core Frequency
Unit
Notes
667 MHz
800 MHz
1000 MHz
1067 MHz
Min
Max
Min
Max
Min
Max
Min
Max
e500 core processor frequency
667
800
667
1000
667
1067
MHz
1, 2
Notes:
1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK
frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating
frequencies. Refer to Section 19.2, “CCB/SYSCLK PLL Ratio,and Section 19.3, “e500 Core PLL Ratio,for ratio settings.
2. The minimum e500 core frequency is based on the minimum platform frequency of 333 MHz.
Table 63. MPC8544EPinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power
Supply
Notes
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