参数资料
型号: MPC8544ECVTALGB
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 667 MHz, RISC PROCESSOR, PBGA783
封装: 29 X 29 MM, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-783
文件页数: 85/120页
文件大小: 1321K
代理商: MPC8544ECVTALGB
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
67
High-Speed Serial Interfaces (HSSI)
To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic)
transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing
that goes between 2.5 V and 2.0 V. Using these values, the peak-to-peak voltage swing of each signal (TD
or TD) is 500 mV p-p, which is referred as the single-ended swing for each signal. In this example, since
the differential signaling environment is fully symmetrical, the transmitter output’s differential swing
(VOD) has the same amplitude as each signal’s single-ended swing. The differential output signal ranges
between 500 mV and –500 mV, in other words, VOD is 500 mV in one phase and –500 mV in the other
phase. The peak differential voltage (VDIFFp) is 500 mV. The peak-to-peak differential voltage (VDIFFp-p)
is 1000 mV p-p.
16.2
SerDes Reference Clocks
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by
the corresponding SerDes lanes. The SerDes reference clocks inputs are SD1_REF_CLK and
SD1_REF_CLK for PCI Express1, PCI Express2. SD2_REF_CLK, and SD2_REF_CLK for the PCI
Express3 or SGMII interface, respectively. The following sections describe the SerDes reference clock
requirements and some application information.
16.2.1
SerDes Reference Clock Receiver Characteristics
Figure 45 shows a receiver reference diagram of the SerDes reference clocks.
The supply voltage requirements for XVDD_SRDS2 are specified in Table 1 and Table 2.
SerDes reference clock receiver reference circuit structure
—The SDn_REF_CLK and SDn_REF_CLK are internally AC-coupled differential inputs as
shown in Figure 45. Each differential clock input (SDn_REF_CLK or SDn_REF_CLK) has a
50-
Ω termination to SGND_SRDSn (xcorevss) followed by on-chip AC-coupling.
— The external reference clock driver must be able to drive this termination.
— The SerDes reference clock input can be either differential or single-ended. Refer to the
differential mode and single-ended mode description below for further detailed requirements.
The maximum average current requirement that also determines the common mode voltage range:
— When the SerDes reference clock differential inputs are DC coupled externally with the clock
driver chip, the maximum average current allowed for each input pin is 8 mA. In this case, the
exact common mode input voltage is not critical as long as it is within the range allowed by the
maximum average current of 8 mA (refer to the following bullet for more detail), since the
input is AC-coupled on-chip.
— This current limitation sets the maximum common mode input voltage to be less than 0.4 V
(0.4 V/50 = 8 mA) while the minimum common mode input level is 0.1 V above
SGND_SRDSn (xcorevss). For example, a clock with a 50/50 duty cycle can be produced by
a clock driver with output driven by its current source from 0mA to 16mA (0–0.8 V), such that
each phase of the differential input has a single-ended swing from 0 V to 800 mV with the
common mode voltage at 400 mV.
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