参数资料
型号: MPC8544EVTALGB
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 667 MHz, RISC PROCESSOR, PBGA783
封装: 29 X 29 MM, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-783
文件页数: 91/120页
文件大小: 1321K
代理商: MPC8544EVTALGB
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 2
72
Freescale Semiconductor
High-Speed Serial Interfaces (HSSI)
Figure 51. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)
Figure 52 shows the SerDes reference clock connection reference circuits for a single-ended clock driver.
It assumes the DC levels of the clock driver are compatible with MPC8544E SerDes reference clock
input’s DC requirement.
Figure 52. Single-Ended Connection (Reference Only)
16.2.4
AC Requirements for SerDes Reference Clocks
The clock driver selected should provide a high quality reference clock with low phase noise and
cycle-to-cycle jitter. Phase noise less than 100 kHz can be tracked by the PLL and data recovery loops and
is less of a problem. Phase noise above 15 MHz is filtered by the PLL. The most problematic phase noise
occurs in the 1–15 MHz range. The source impedance of the clock driver should be 50
Ω to match the
transmission line and reduce reflections which are a source of noise to the system.
50
Ω
50
Ω
SD
n_REF_CLK
SD
n_REF_CLK
Clock Driver
100
Ω differential PWB trace
SerDes Refer.
CLK Receiver
Clock Driver
CLK_Out
LVPECL CLK
Driver Chip
R2
R1
10nF
MPC8544E
50
Ω
50
Ω
SD
n_REF_CLK
SD
n_REF_CLK
100
Ω differential PWB trace
SerDes Refer.
CLK Receiver
Clock Driver
CLK_Out
Single-Ended
CLK Driver Chip
33
Ω
Total 50
Ω. Assume clock driver’s
output impedance is about 16
Ω.
50
Ω
MPC8544E
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