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参数资料
型号： MPC8545EVTANGB
厂商： Freescale Semiconductor
文件页数： 138/151页
文件大小： 0K
描述： MPU POWERQUICC III 783-PBGA
标准包装： 1
系列： MPC85xx
处理器类型： 32-位 MPC85xx PowerQUICC III
速度： 800MHz
电压： 1.1V
安装类型： 表面贴装
封装/外壳： 783-BBGA，FCBGA
供应商设备封装： 783-FCPBGA（29x29）
包装： 托盘
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
Freescale Semiconductor
87
Serial RapidIO
components are included in this requirement. The reference impedance for return loss measurements is
100-
resistive for differential return loss and 25- resistive for common mode.
Table 66. Receiver AC Timing Specifications—1.25 GBaud
Characteristic
Symbol
Range
Unit
Notes
Min
Max
Differential input voltage
VIN
200
1600
mVp-p
Measured at receiver
Deterministic jitter tolerance
JD
0.37
—
UI p-p
Measured at receiver
Combined deterministic and random
jitter tolerance
JDR
0.55
—
UI p-p
Measured at receiver
Total jitter tolerance1
JT
0.65
—
UI p-p
Measured at receiver
Multiple input skew
SMI
—
24
ns
Skew at the receiver input between lanes
of a multilane link
Bit error rate
BER
—
10–12
——
Unit interval
UI
800
ps
±100 ppm
Note:
1. Total jitter is composed of three components, deterministic jitter, random jitter, and single frequency sinusoidal jitter. The
sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 53. The sinusoidal jitter component
is included to ensure margin for low frequency jitter, wander, noise, crosstalk, and other variable system effects.
Table 67. Receiver AC Timing Specifications—2.5 GBaud
Characteristic
Symbol
Range
Unit
Notes
Min
Max
Differential input voltage
VIN
200
1600
mVp-p
Measured at receiver
Deterministic jitter tolerance
JD
0.37
—
UI p-p
Measured at receiver
Combined deterministic and random
jitter tolerance
JDR
0.55
—
UI p-p
Measured at receiver
Total jitter tolerance1
JT
0.65
—
UI p-p
Measured at receiver
Multiple input skew
SMI
—
24
ns
Skew at the receiver input between lanes
of a multilane link
Bit error rate
BER
—
10–12
—
Unit interval
UI
400
ps
±100 ppm
Note:
1. Total jitter is composed of three components, deterministic jitter, random jitter, and single frequency sinusoidal jitter. The
sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 53. The sinusoidal jitter component
is included to ensure margin for low frequency jitter, wander, noise, crosstalk, and other variable system effects.
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