- 您现在的位置：买卖IC网 > PDF目录80354 > MPC8548EPXAQHA (FREESCALE SEMICONDUCTOR INC) 32-BIT, 1000 MHz, MICROPROCESSOR, PBGA783 PDF资料下载
参数资料
| 型号： | MPC8548EPXAQHA |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 1000 MHz, MICROPROCESSOR, PBGA783 |
| 封装： | 29 X 29 MM, 1 MM PITCH, FLIP CHIP, PLASTIC, BGA-783 |
| 文件页数： | 127/142页 |
| 文件大小： | 1504K |
| 代理商： | MPC8548EPXAQHA |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页当前第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
85
Serial RapidIO
is specified as the test pattern for use in eye pattern and jitter measurements. Annex 48B of IEEE Std.
802.3ae-2002 is recommended as a reference for additional information on jitter test methods.
17.9.1
Eye Template Measurements
For the purpose of eye template measurements, the effects of a single-pole high pass filter with a 3 dB point
at (baud frequency)/1667 is applied to the jitter. The data pattern for template measurements is the
continuous jitter test pattern (CJPAT) defined in Annex 48A of IEEE 802.3ae. All lanes of the LP-serial
link shall be active in both the transmit and receive directions, and opposite ends of the links shall use
asynchronous clocks. Four lane implementations shall use CJPAT as defined in Annex 48A. Single lane
implementations shall use the CJPAT sequence specified in Annex 48A for transmission on lane 0. The
amount of data represented in the eye shall be adequate to ensure that the bit error ratio is less than 10–12.
The eye pattern shall be measured with AC coupling and the compliance template centered at 0 V
differential. The left and right edges of the template shall be aligned with the mean zero crossing points of
the measured data eye. The load for this test shall be 100-
Ω resistive ± 5% differential to 2.5 GHz.
17.9.2
Jitter Test Measurements
For the purpose of jitter measurement, the effects of a single-pole high pass filter with a 3 dB point at (baud
frequency)/1667 is applied to the jitter. The data pattern for jitter measurements is the Continuous Jitter test
pattern (CJPAT) pattern defined in Annex 48A of IEEE 802.3ae. All lanes of the LP-serial link shall be
active in both the transmit and receive directions, and opposite ends of the links shall use asynchronous
clocks. Four lane implementations shall use CJPAT as defined in Annex 48A. Single lane implementations
shall use the CJPAT sequence specified in Annex 48A for transmission on lane 0. Jitter shall be measured
with AC coupling and at 0 V differential. Jitter measurement for the transmitter (or for calibration of a jitter
tolerance setup) shall be performed with a test procedure resulting in a BER curve such as that described
in Annex 48B of IEEE 802.3ae.
17.9.3
Transmit Jitter
Transmit jitter is measured at the driver output when terminated into a load of 100
Ω resistive ± 5%
differential to 2.5 GHz.
17.9.4
Jitter Tolerance
Jitter tolerance is measured at the receiver using a jitter tolerance test signal. This signal is obtained by first
producing the sum of deterministic and random jitter defined in Section 17.7, “Receiver Specifications,”
and then adjusting the signal amplitude until the data eye contacts the 6 points of the minimum eye opening
of the receive template shown in Figure 54 and Table 65. Note that for this to occur, the test signal must
have vertical waveform symmetry about the average value and have horizontal symmetry (including jitter)
about the mean zero crossing. Eye template measurement requirements are as defined above. Random
jitter is calibrated using a high pass filter with a low frequency corner at 20 MHz and a 20 dB/decade
roll-off below this. The required sinusoidal jitter specified in Section 17.7, “Receiver Specifications,” is
then added to the signal and the test load is replaced by the receiver being tested.
相关PDF资料 |
PDF描述 |
|---|---|
| MPC8548EVTAVJB | 32-BIT, 1500 MHz, MICROPROCESSOR, PBGA783 |
| MPC8548PXAQHA | 32-BIT, 1000 MHz, MICROPROCESSOR, PBGA783 |
| MPC8548VUAVH | 32-BIT, 1500 MHz, MICROPROCESSOR, CBGA783 |
| M30263F8AFP-U7 | 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PDSO42 |
| MB95F106AJWPMC1 | 16-BIT, FLASH, 16.25 MHz, RISC MICROCONTROLLER, PQFP64 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC8548EPXATGA | 制造商:Freescale Semiconductor 功能描述:MPC85XX RISC 32-BIT CMOS 1.2GHZ 1.8V/2.5V/3.3V 783-PIN BGA T - Bulk |
| MPC8548EPXATGB | 功能描述:微处理器 - MPU FG PQ38 8548 RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8548EPXAUJA | 制造商:Freescale Semiconductor 功能描述:MPC85XX RISC 32-BIT CMOS 1.333GHZ 1.8V/2.5V/3.3V 783-PIN BGA - Bulk |
| MPC8548EPXAUJB | 功能描述:微处理器 - MPU FG PQ38 8548 RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8548EPXAUJC | 功能描述:微处理器 - MPU REV2.1.3 FG part 1333 RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
发布紧急采购，3分钟左右您将得到回复。