参数资料
型号: MPC8555CPXAJEX
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 533 MHz, RISC PROCESSOR, PBGA783
封装: 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, FLIP CHIP, PLASTIC, BGA-783
文件页数: 44/88页
文件大小: 1244K
代理商: MPC8555CPXAJEX
MPC8555E PowerQUICC III Integrated Communications Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
49
JTAG
11 JTAG
This section describes the AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the
MPC8555E.
Table 38 provides the JTAG AC timing specifications as defined in Figure 32 through Figure 35.
Table 38. JTAG AC Timing Specifications (Independent of SYSCLK) 1
At recommended operating conditions (see Table 2).
Parameter
Symbol 2
Min
Max
Unit
Notes
JTAG external clock frequency of operation
fJTG
0
33.3
MHz
JTAG external clock cycle time
t JTG
30
ns
JTAG external clock pulse width measured at 1.4 V
tJTKHKL
15
ns
JTAG external clock rise and fall times
tJTGR & tJTGF
02
ns
TRST assert time
tTRST
25
ns
3
Input setup times:
Boundary-scan data
TMS, TDI
tJTDVKH
tJTIVKH
4
0
ns
4
Input hold times:
Boundary-scan data
TMS, TDI
tJTDXKH
tJTIXKH
20
25
ns
4
Valid times:
Boundary-scan data
TDO
tJTKLDV
tJTKLOV
4
20
25
ns
5
Output hold times:
Boundary-scan data
TDO
tJTKLDX
tJTKLOX
ns
5
JTAG external clock to output high impedance:
Boundary-scan data
TDO
tJTKLDZ
tJTKLOZ
3
19
9
ns
5, 6
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in
question. The output timings are measured at the pins. All output timings assume a purely resistive 50-
Ω load (see
Figure 31). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH
symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the
tJTG clock reference (K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to
the time data input signals (D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that,
in general, the clock reference symbol representation is based on three letters representing the clock of a particular
functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to tTCLK.
5. Non-JTAG signal output timing with respect to tTCLK.
6. Guaranteed by design.
相关PDF资料
PDF描述
MPC8555CVTAJFX 32-BIT, 533 MHz, RISC PROCESSOR, PBGA783
MPC8555PXALDX 32-BIT, 667 MHz, RISC PROCESSOR, PBGA783
MPC8555EPXALFX 32-BIT, 667 MHz, RISC PROCESSOR, PBGA783
MPC8555CVTAKDX 32-BIT, 600 MHz, RISC PROCESSOR, PBGA783
MPC8555PXAQFX 32-BIT, 1000 MHz, RISC PROCESSOR, PBGA783
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