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参数资料
| 型号： | MPC8560CPXALFB |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 667 MHz, RISC PROCESSOR, PBGA783 |
| 封装： | 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, FLIP CHIP, PLASTIC, BGA-783 |
| 文件页数： | 73/108页 |
| 文件大小： | 2170K |
| 代理商： | MPC8560CPXALFB |
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MPC8560 Integrated Processor Hardware Specifications, Rev. 3.1
Freescale Semiconductor
67
RapidIO
The eye pattern for a data signal is generated by making a large number of recordings of the signal and then
overlaying the recordings. The number of recordings used to generate the eye shall be large enough that further
increasing the number of recordings used does not cause the resulting eye pattern to change from one that complies
with the RapidIO transmit mask to one that does not. Each data signal in the interface shall be carrying random or
pseudo-random data when the recordings are made. If pseudo-random data is used, the length of the pseudo-random
sequence (repeat length) shall be long enough that increasing the length of the sequence does not cause the resulting
eye pattern to change from one that complies with the RapidIO transmit mask to one that does not comply with the
mask. The data carried by any given data signal in the interface may not be correlated with the data carried by any
other data signal in the interface. The zero-crossings of the clock associated with a data signal shall be used as the
timing reference for aligning the multiple recordings of the data signal when the recordings are overlaid.
While the method used to make the recordings and overlay them to form the eye pattern is not specified, the method
used shall be demonstrably equivalent to the following method. The signal under test is repeatedly recorded with a
digital oscilloscope in infinite persistence mode. Each recording is triggered by a zero-crossing of the clock
associated with the data signal under test. Roughly half of the recordings are triggered by positive-going clock
zero-crossings and roughly half are triggered by negative-going clock zero-crossings. Each recording is at least 1.9
UI in length (to ensure that at least one complete eye is formed) and begins 0.5 UI before the trigger point (0.5 UI
before the associated clock zero-crossing). Depending on the length of the individual recordings used to generate
the eye pattern, one or more complete eyes will be formed. Regardless of the number of eyes, the eye whose center
is immediately to the right of the trigger point is the eye used for compliance testing.
An example of an eye pattern generated using the above method with recordings 3 UI in length is shown in
Figure 45. In this example, there is no skew between the signal under test and the associated clock used to trigger
the recordings. If skew was present, the eye pattern would be shifted to the left or right relative to the oscilloscope
trigger point.
.
Figure 45. Example Driver Output Eye Pattern
13.3.2 RapidIO Receiver AC Timing Specifications
The RapidIO receiver AC timing specifications are provided in Table 50. A receiver shall comply with the
specifications for each data rate/frequency for which operation of the receiver is specified. Unless otherwise
specified, these specifications are subject to the following conditions.
0
+
–
V
OD
0.5 UI
1.0 UI
Oscilloscope
(Recording)
Trigger Point
Eye Pattern
Eye Used for
Compliance
Testing
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| MPC8560CVT667LB | 功能描述:微处理器 - MPU PQ 3 8560 Dracom RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
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