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参数资料
型号： MPC8568ECVTAUJJA
厂商： FREESCALE SEMICONDUCTOR INC
元件分类： 微控制器/微处理器
英文描述： 32-BIT, 1333 MHz, RISC PROCESSOR, PBGA1023
封装： 33 X 33 MM, 2.75 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, FCBGA-1023
文件页数： 35/139页
文件大小： 1449K
代理商： MPC8568ECVTAUJJA
MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
13
Electrical Characteristics
The core voltage must always be provided at nominal 1.1V. (See Table 3 for actual recommended core
voltage). Voltage to the processor interface I/Os are provided through separate sets of supply pins and must
be provided at the voltages shown in Table 3. The input voltage threshold scales with respect to the
associated I/O supply voltage. OVDD and LVDD based receivers are simple CMOS I/O circuits and satisfy
appropriate LVCMOS type specifications. The DDR SDRAM interface uses a single-ended differential
receiver referenced the externally supplied MVREF signal (nominally set to GVDD/2) as is appropriate for
the SSTL2 electrical signaling standard.
2.1.3
Output Driver Characteristics
Table 4 provides information on the characteristics of the output driver strengths. The values are
preliminary estimates.
2.2
Power Sequencing
The MPC8568E requires its power rails to be applied in specific sequence in order to ensure proper device
operation. These requirements are as follows for power up:
1. VDD, AVDD_n, BVDD, SCOREVDD, LVDD, TVDD, XVDD, OVDD
2. GVDD
All supplies must be at their stable values within 50 ms.
Table 4. Output Drive Capability
Driver Type
Programmable
Output Impedance
(
Ω)
Supply
Voltage
Notes
Local bus interface utilities signals
25
BVDD = 3.3 V
BVDD = 2.5 V
1
45(default)
BVDD = 3.3 V
BVDD = 2.5 V
PCI signals
25
OVDD = 3.3 V
2
42 (default)
DDR signal
20
GVDD = 2.5 V
—
DDR2 signal
16
32 (half strength mode)
GVDD = 1.8 V
—
eTSEC 10/100/1000 signals
42
L/TVDD = 2.5/3.3 V
—
DUART, system control, JTAG
42
OVDD = 3.3 V
—
I2C
150
OVDD = 3.3 V
—
Notes:
1. The drive strength of the local bus interface is determined by the configuration of the appropriate bits in PORIMPSCR.
2. The drive strength of the PCI interface is determined by the setting of the PCI_GNT[1] signal at reset.
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