参数资料
型号: MPC8569VTAQLJA
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: RISC PROCESSOR, PBGA783
封装: 29 X 29 MM, 1 MM PITCH, PLASTIC, BGA-783
文件页数: 66/126页
文件大小: 2847K
代理商: MPC8569VTAQLJA
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
Input Clocks
Freescale Semiconductor
44
The following table provides the system clock (SYSCLK) AC timing specifications.
2.3.1
Spread Spectrum Sources
Spread spectrum clock sources are an increasingly popular way to control electromagnetic interference emissions (EMI) by
spreading the emitted noise to a wider spectrum and reducing the peak noise magnitude in order to meet industry and
government requirements. These clock sources intentionally add long-term jitter to diffuse the EMI spectral content. The jitter
specification given in below table considers short-term (cycle-to-cycle) jitter only. The clock generator’s cycle-to-cycle output
jitter should meet the MPC8569E input cycle-to-cycle jitter requirement. Frequency modulation and spread are separate
concerns; the MPC8569E is compatible with spread spectrum sources if the recommendations listed in the following table are
observed.
CAUTION
The processor’s minimum and maximum SYSCLK and core frequencies must not be
exceeded regardless of the type of clock source. Therefore, systems in which the processor
is operated at its maximum rated e500 core frequency should avoid violating the stated
limits by using down-spreading only.
Table 10. SYSCLK AC Timing Specifications
At recommended operating conditions with OVDD = 3.3 V ± 165 mV
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Notes
SYSCLK frequency
fSYSCLK
66
133
MHz
1, 2
SYSCLK cycle time
tSYSCLK
7.5
15.15
ns
1, 2
SYSCLK duty cycle
tKHK/
tSYSCLK/DDRCLK
40
60
%
2
SYSCLK slew rate
1
4
V/ns
3
SYSCLK peak period jitter
± 150
ps
SYSCLK jitter phase noise at –56 dBc
500
KHz
4
AC Input Swing Limits at 3.3 V OVDD
ΔVAC
1.9
V
Notes:
1. Caution: The relevant clock ratio settings must be chosen such that the resulting SYSCLK frequency do not exceed their
respective maximum or minimum operating frequencies.
2. Measured at the rising edge and/or the falling edge at OVDD/2.
3. Slew rate as measured from ±0.3
ΔVAC at the center of peak to peak voltage at clock input.
4. Phase noise is calculated as FFT of TIE jitter.
Table 11. Spread Spectrum Clock Source Recommendations
At recommended operating conditions with OVDD = 3.3 V ± 165 mV.
Parameter
Min
Max
Unit
Notes
Frequency modulation
60
kHz
Frequency spread
1.0
%
1, 2
Notes:
1. SYSCLK frequencies that result from frequency spreading and the resulting core frequency must meet the minimum and
maximum specifications given in Table 10.
2. Maximum spread spectrum frequency may not result in exceeding any maximum operating frequency of the device.
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