参数资料
型号: MPC8572CLVTAVNE
厂商: Freescale Semiconductor
文件页数: 28/138页
文件大小: 0K
描述: MPU POWERQUICC III 1023FCPBGA
标准包装: 1
系列: MPC85xx
处理器类型: 32-位 MPC85xx PowerQUICC III
速度: 1.5GHz
电压: 1.1V
安装类型: 表面贴装
封装/外壳: 1023-BBGA,FCBGA
供应商设备封装: 1023-FCPBGA(33x33)
包装: 托盘
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
123
System Design Information
Vf = Voltage forward biased
VH = Diode voltage while IH is flowing
VL = Diode voltage while IL is flowing
IH = Larger diode bias current
IL = Smaller diode bias current
q = Charge of electron (1.6 x 10 –19 C)
n = Ideality factor (normally 1.0)
K = Boltzman’s constant (1.38 x 10–23 Joules/K)
T = Temperature (Kelvins)
The ratio of IH to IL is usually selected to be 10:1. The above simplifies to the following:
Solving for T, the equation becomes:
21 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8572E.
21.1
System Clocking
The platform PLL generates the platform clock from the externally supplied SYSCLK input. The
frequency ratio between the platform and SYSCLK is selected using the platform PLL ratio configuration
bits as described in Section 19.2, “CCB/SYSCLK PLL Ratio.The MPC8572E includes seven PLLs, with
the following functions:
Two core PLLs have ratios that are individually configurable. Each e500 core PLL generates the
core clock as a slave to the platform clock. The frequency ratio between the e500 core clock and
the platform clock is selected using the e500 PLL ratio configuration bits as described in
The DDR complex PLL generates the clocking for the DDR controllers.
The local bus PLL generates the clock for the local bus.
The PLL for the SerDes1 module is used for PCI Express and Serial Rapid IO interfaces.
The PLL for the SerDes2 module is used for the SGMII interface.
VH – VL = 1.986 × 10
–4 × nT
nT =
VH – VL
__________
1.986
× 10–4
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