参数资料
型号: MPC8572EVTATLD
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 1200 MHz, MICROPROCESSOR, PBGA1023
封装: 33 X 33 MM, LEAD FREE, PLASTIC, FCBGA-1023
文件页数: 119/138页
文件大小: 1502K
代理商: MPC8572EVTATLD
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
81
High-Speed Serial Interfaces (HSSI)
Figure 52. Differential Measurement Points for Rise and Fall Time
Figure 53. Single-Ended Measurement Points for Rise and Fall Time Matching
The other detailed AC requirements of the SerDes Reference Clocks is defined by each interface protocol
based on application usage. Refer to the following sections for detailed information:
Rising edge rate (SDn_REF_CLK) to falling edge rate
(SDn_REF_CLK) matching
Rise-Fall
Matching
—20
%
1, 4
Notes:
1. Measurment taken from single ended waveform.
2. Measurment taken from differential waveform.
3. Measured from -200 mV to +200 mV on the differential waveform (derived from SDn_REF_CLK minus SDn_REF_CLK). The
signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is centered
on the differential zero crossing. See Figure 52.
4. Matching applies to rising edge rate for SDn_REF_CLK and falling edge rate for SDn_REF_CLK. It is measured using a 200
mV window centered on the median cross point where SDn_REF_CLK rising meets SDn_REF_CLK falling. The median cross
point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The Rise Edge Rate
of SDn_REF_CLK should be compared to the Fall Edge Rate of SDn_REF_CLK, the maximum allowed difference should not
exceed 20% of the slowest edge rate. See Figure 53.
Table 57. SerDes Reference Clock Common AC Parameters (continued)
At recommended operating conditions with XVDD_SRDS1 or XVDD_SRDS2 = 1.1V ± 5%.
Parameter
Symbol
Min
Max
Unit
Notes
VIH = +200 mV
VIL = -200 mV
0.0 V
SD
n_REF_CLK
minus
SD
n_REF_CLK
SD
n_REF_CLK
SD
n_REF_CLK
SD
n_REF_CLK
SD
n_REF_CLK
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