收藏本站
参数资料
型号： MPC8572EVTAVND
厂商： Freescale Semiconductor
文件页数： 23/138页
文件大小： 0K
描述： MPU POWERQUICC III 1023-PBGA
标准包装： 1
系列： MPC85xx
处理器类型： 32-位 MPC85xx PowerQUICC III
速度： 1.5GHz
电压： 1.1V
安装类型： 表面贴装
封装/外壳： 1023-BBGA，FCBGA
供应商设备封装： 1023-FCPBGA（33x33）
包装： 托盘
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
119
Clocking
Table 80 describes the clock ratio between e500 Core0 and the e500 core complex bus (CCB). This ratio
is determined by the binary value of LBCTL, LALE and LGPL2/LOE/LFRE at power up, as shown in
Table 80.
Table 81 describes the clock ratio between e500 Core1 and the e500 core complex bus (CCB). This ratio
is determined by the binary value of LWE[0]/LBS[0]/LFWE, UART_SOUT[1], and READY_P1 signals
at power up, as shown in Table 81.
19.4
DDR/DDRCLK PLL Ratio
The dual DDR memory controller complexes can be synchronous with, or asynchronous to, the CCB,
depending on configuration.
Table 82 describes the clock ratio between the DDR memory controller complexes and the DDR PLL
reference clock, DDRCLK, which is not the memory bus clock. The DDR memory controller complexes
clock frequency is equal to the DDR data rate.
When synchronous mode is selected, the memory buses are clocked at half the CCB clock rate. The default
mode of operation is for the DDR data rate for both DDR controllers to be equal to the CCB clock rate in
synchronous mode, or the resulting DDR PLL rate in asynchronous mode.
In asynchronous mode, the DDR PLL rate to DDRCLK ratios listed in Table 82 reflects the DDR data rate
to DDRCLK ratio, because the DDR PLL rate in asynchronous mode means the DDR data rate resulting
from DDR PLL output.
Table 80. e500 Core0 to CCB Clock Ratio
Binary Value of
LBCTL, LALE,
LGPL2/LOE/LFRE
Signals
e500 Core0:CCB Clock Ratio
Binary Value of
LBCTL, LALE,
LGPL2/LOE/LFRE
Signals
e500 Core0:CCB Clock Ratio
000
Reserved
100
2:1
001
Reserved
101
5:2 (2.5:1)
010
Reserved
110
3:1
011
3:2 (1.5:1)
111
7:2 (3.5:1)
Table 81. e500 Core1 to CCB Clock Ratio
Binary Value of
LWE[0]/LBS[0]/
LFWE, UART_SOUT[1],
READY_P1 Signals
e500 Core1:CCB Clock Ratio
Binary Value of
LWE[0]/LBS[0]/
LFWE, UART_SOUT[1],
READY_P1 Signals
e500 Core1:CCB Clock Ratio
000
Reserved
100
2:1
001
Reserved
101
5:2 (2.5:1)
010
Reserved
110
3:1
011
3:2 (1.5:1)
111
7:2 (3.5:1)
相关PDF资料
PDF描述
FMC50DRXN CONN EDGECARD 100PS DIP .100 SLD
FMC49DRXI CONN EDGECARD 98POS DIP .100 SLD
FMC50DRXH CONN EDGECARD 100PS DIP .100 SLD
MPC8572EPXAVND MPU POWERQUICC III 1023-PBGA
ABB108DHBS CONN EDGECARD 216PS R/A .050 SLD
相关代理商/技术参数
参数描述
MPC8572EVTAVNE 功能描述:微处理器 - MPU 38H R211 Enc NoPb 1500 RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324
MPC8572LPXARLD 功能描述:微处理器 - MPU CSM SNPB 1067 LOW PWR RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324
MPC8572LPXARLE 制造商:Freescale Semiconductor 功能描述:38H R211 NOE SNPB 1067LP - Bulk
MPC8572LPXATLD 功能描述:微处理器 - MPU CSM SNPB 1200 LOW PWR RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324
MPC8572LPXATLE 制造商:Freescale Semiconductor 功能描述:38H R211 NOE SNPB 1200LP - Bulk
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*