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| 型号： | MPC860PVR66D4R2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 13/78页 |
| 文件大小： | 0K |
| 描述： | IC MPU POWERQUICC 66MHZ 357PBGA |
| 标准包装： | 180 |
| 系列： | MPC8xx |
| 处理器类型： | 32-位 MPC8xx PowerQUICC |
| 速度： | 66MHz |
| 电压： | 3.3V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 357-BBGA |
| 供应商设备封装： | 357-PBGA（25x25） |
| 包装： | 带卷 (TR) |
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MPC860 PowerQUICC Family Hardware Specifications, Rev. 9
20
Freescale Semiconductor
Bus Signal Timing
B35
A(0:31), BADDR(28:30) to CS valid—as
requested by control bit BST4 in the
corresponding word in UPM
5.58
—
4.25
—
3.00
—
1.79
—
ns
B35a
A(0:31), BADDR(28:30), and D(0:31) to BS
valid—as requested by control bit BST1 in
the corresponding word in UPM
13.15
—
10.50
—
8.00
—
5.58
—
ns
B35b
A(0:31), BADDR(28:30), and D(0:31) to BS
valid—as requested by control bit BST2 in
the corresponding word in UPM
20.73
—
16.75
—
13.00
—
9.36
—
ns
B36
A(0:31), BADDR(28:30), and D(0:31) to
GPL valid—as requested by control bit GxT4
in the corresponding word in UPM
5.58
—
4.25
—
3.00
—
1.79
—
ns
B37
UPWAIT valid to CLKOUT falling edge9
6.00
—
6.00
—
6.00
—
6.00
—
ns
B38
CLKOUT falling edge to UPWAIT valid9
1.00
—
1.00
—
1.00
—
1.00
—
ns
B39
AS valid to CLKOUT rising edge10
7.00
—
7.00
—
7.00
—
7.00
—
ns
B40
A(0:31), TSIZ(0:1), RD/WR, BURST, valid to
CLKOUT rising edge
7.00
—
7.00
—
7.00
—
7.00
—
ns
B41
TS valid to CLKOUT rising edge (setup time)
7.00
—
7.00
—
7.00
—
7.00
—
ns
B42
CLKOUT rising edge to TS valid (hold time)
2.00
—
2.00
—
2.00
—
2.00
—
ns
B43
AS negation to memory controller signals
negation
—TBD
ns
1 Phase and frequency jitter performance results are only valid if the input jitter is less than the prescribed value.
2 If the rate of change of the frequency of EXTAL is slow (that is, it does not jump between the minimum and maximum values
in one cycle) or the frequency of the jitter is fast (that is, it does not stay at an extreme value for a long time) then the maximum
allowed jitter on EXTAL can be up to 2%.
3 The timings specified in B4 and B5 are based on full strength clock.
4 The timing for BR output is relevant when the MPC860 is selected to work with external bus arbiter. The timing for BG output
is relevant when the MPC860 is selected to work with internal bus arbiter.
5 The timing required for BR input is relevant when the MPC860 is selected to work with internal bus arbiter. The timing for BG
input is relevant when the MPC860 is selected to work with external bus arbiter.
6 The D(0:31) and DP(0:3) input timings B18 and B19 refer to the rising edge of the CLKOUT in which the TA input signal is
asserted.
7 The D(0:31) and DP(0:3) input timings B20 and B21 refer to the falling edge of the CLKOUT. This timing is valid only for read
accesses controlled by chip-selects under control of the UPM in the memory controller, for data beats where DLT3 = 1 in the
UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)
8 The timing B30 refers to CS when ACS = 00 and to WE(0:3) when CSNT = 0.
9 The signal UPWAIT is considered asynchronous to the CLKOUT and synchronized internally. The timings specified in B37 and
B38 are specified to enable the freeze of the UPM output signals as described in Figure 18.
10 The AS signal is considered asynchronous to the CLKOUT. The timing B39 is specified in order to allow the behavior specified
in Figure 21.
Table 7. Bus Operation Timings (continued)
Num
Characteristic
33 MHz
40 MHz
50 MHz
66 MHz
Unit
Min
Max
Min
Max
Min
Max
Min
Max
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