参数资料
型号: MPC866TCVR100A
厂商: Freescale Semiconductor
文件页数: 8/96页
文件大小: 0K
描述: IC MPU POWERQUICC 100MHZ 357PBGA
标准包装: 44
系列: MPC8xx
处理器类型: 32-位 MPC8xx PowerQUICC
速度: 100MHz
电压: 1.8V
安装类型: 表面贴装
封装/外壳: 357-BBGA
供应商设备封装: 357-PBGA(25x25)
包装: 托盘
MPC866/MPC859 Hardware Specifications, Rev. 2
16
Freescale Semiconductor
Bus Signal Timing
This recommendation particularly applies to the address and data buses. Maximum PC trace lengths of 6” are
recommended. Capacitance calculations should consider all device loads as well as parasitic capacitances due to the
PC traces. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher
capacitive loads because these loads create higher transient currents in the VDD and GND circuits. Pull up all unused
inputs or signals that will be inputs during reset. Special care should be taken to minimize the noise levels on the
PLL supply pins. For more information, please refer to Section 14.4.3, Clock Synthesizer Power (VDDSYN,
VSSSYN, VSSSYN1), in the MPC866 User’s Manual.
10 Bus Signal Timing
The maximum bus speed supported by the MPC866/859 is 66 MHz. Higher-speed parts must be operated in
half-speed bus mode (for example, an MPC866/859 used at 100 MHz must be configured for a 50-MHz bus).
Table 7 and Table 8 show the frequency ranges for standard part frequencies.
Table 9 shows the timings for the MPC866/859 at 33, 40, 50, and 66 MHz bus operation. The timing for the
MPC866/859 bus shown in this table assumes a 50-pF load for maximum delays and a 0-pF load for minimum
delays. CLKOUT assumes a 100-pF load maximum delay.
Table 7. Frequency Ranges for Standard Part Frequencies (1:1 Bus Mode)
Part Freq
50 MHz
66 MHz
Min
Max
Min
Max
Core
40
50
40
66.67
Bus
40
50
40
66.67
Table 8. Frequency Ranges for Standard Part Frequencies (2:1 Bus Mode)
Part
Freq
50 MHz
66 MHz
100 MHz
133 MHz
Min
Max
Min
Max
Min
Max
Min
Max
Core
40
50
40
66.67
40
100
40
133.34
Bus
20
25
20
33.33
20
50
20
66.67
Table 9. Bus Operation Timings
Num
Characteristic
33 MHz
40 MHz
50 MHz
66 MHz
Unit
Min
Max
Min
Max
Min
Max
Min
Max
B1
Bus Period (CLKOUT) See Table 7
—————
ns
B1a
EXTCLK to CLKOUT phase skew
– 2
+2
– 2
+2
– 2
+2
– 2
+2
ns
B1b
CLKOUT frequency jitter peak-to-peak
1
1
1
1
ns
B1c
Frequency jitter on EXTCLK
0.50
0.50
0.50
0.50
%
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