参数资料
型号: MPC870VR133
厂商: Freescale Semiconductor
文件页数: 17/84页
文件大小: 0K
描述: IC MPU POWERQUICC 133MHZ 256PBGA
标准包装: 60
系列: MPC8xx
处理器类型: 32-位 MPC8xx PowerQUICC
速度: 133MHz
电压: 3.3V
安装类型: 表面贴装
封装/外壳: 256-BGA
供应商设备封装: 256-PBGA(23x23)
包装: 托盘
MPC875/MPC870 PowerQUICC Hardware Specifications, Rev. 4
24
Freescale Semiconductor
Bus Signal Timing
B42
CLKOUT rising edge to TS valid (hold time)
(MIN = 0.00
× B1 + 2.00)
2.00
2.00
2.00
2.00
ns
B43
AS negation to memory controller signals
negation (MAX = TBD)
TBD
TBD
TBD
TBD
ns
1 For part speeds above 50 MHz, use 9.80 ns for B11a.
2 The timing required for BR input is relevant when the MPC875/MPC870 is selected to work with the internal bus arbiter. The
timing for BG input is relevant when the MPC875/MPC870 is selected to work with the external bus arbiter.
3 For part speeds above 50 MHz, use 2 ns for B17.
4 The D(0:31) input timings B18 and B19 refer to the rising edge of the CLKOUT in which the TA input signal is asserted.
5 For part speeds above 50 MHz, use 2 ns for B19.
6 The D(0:31) input timings B20 and B21 refer to the falling edge of the CLKOUT. This timing is valid only for read accesses
controlled by chip-selects under control of the user-programmable machine (UPM) in the memory controller, for data beats
where DLT3 = 1 in the RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)
7 This formula applies to bus operation up to 50 MHz.
8 The timing B30 refers to CS when ACS = 00 and to WE(0:3) when CSNT = 0.
9 The signal UPWAIT is considered asynchronous to the CLKOUT and synchronized internally. The timings specified in B37 and
B38 are specified to enable the freeze of the UPM output signals as described in Figure 20.
10 The AS signal is considered asynchronous to the CLKOUT. The timing B39 is specified in order to allow the behavior specified
Table 10. Bus Operation Timings (continued)
Num
Characteristic
33 MHz
40 MHz
66 MHz
80 MHz
Unit
Min
Max
Min
Max
Min
Max
Min
Max
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