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参数资料
| 型号： | MPC905EF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO16 |
| 封装： | LEAD FREE, PLASTIC, SOIC-16 |
| 文件页数： | 5/8页 |
| 文件大小： | 649K |
| 代理商： | MPC905EF |
MPC905
1:6 PCI CLOCK GENERATOR/FANOUT BUFFR
IDT / ICS PCI CLOCK GENERATOR/FANOUT BUFFER
5
MPC905 REV 4 JANUARY 8, 2008
APPLICATIONS INFORMATION
DRIVING TRANSMISSION LINES
The MPC905 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of approximately 10
the drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to application note AN1091 in the
Timing Solutions data book (DL207/D).
In most high performance clock networks point-to-point
distribution of signals is the method of choice. In a point-to-
point scheme either series terminated or parallel terminated
transmission lines can be used. The parallel technique
terminates the signal at the end of the line with a 50
resistance to VCC/2. This technique draws a fairly high level
of DC current and thus only a single terminated line can be
driven by each output of the MPC905 clock driver. For the
series terminated case however there is no DC current draw,
thus the outputs can drive multiple series terminated lines.
Figure 6 illustrates an output driving a single series
terminated line vs two series terminated lines in parallel.
When taken to its extreme the fanout of the MPC905 clock
driver is effectively doubled due to its capability to drive
multiple lines.
Figure 6. Single versus Dual Transmission Lines
The waveform plots of Figure 7 show the simulation
results of an output driving a single line vs two lines. In both
cases the drive capability of the MPC905 output buffers is
more than sufficient to drive 50
transmission lines on the
incident edge.
Note from the delay measurements in the simulations a
delta of only 43 ps exists between the two differently loaded
outputs. The output waveform in Figure 7 shows a step in the
waveform, this step is caused by the impedance mismatch
seen looking into the driver. The parallel combination of the
40
series resistor plus the output impedance does not
match the parallel combination of the line impedances. The
voltage wave launched down the two lines will equal:
VL = VS (Zo / Rs + Ro + Zo) = 3.0 (25/55) = 1.36 V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.73 V. It will then increment
towards the quiescent 3.0 V in steps separated by one round
trip delay (in this case 4.0 ns).
Figure 7. Single versus Dual Waveforms
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the
situation in Figure 8 should be used. In this case the series
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance the line
impedance is perfectly matched.
Figure 8. Optimized Dual Line Termination
MPC905
OUTPUT
BUFFER
IN
10
RS = 40
ZO = 50
OutA
OutB0
OutB1
ZO = 50
RS = 40
MPC905
OUTPUT
BUFFER
IN
10
3.0
2.5
2.0
1.5
1.0
0.5
0
2
4
6
8
10
12
14
TIME (ns)
OutB
tD = 3.9386
OutA
tD = 3.8956
IN
VOLTA
G
E(V)
10
+ 30 || 30 = 50 ||50
25
= 25
MPC905
OUTPUT
BUFFER
10
RS = 30
ZO = 50
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