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参数资料
| 型号： | MPC9230FN |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 750 MHz, OTHER CLOCK GENERATOR, PQCC28 |
| 封装： | PLASTIC, LCC-28 |
| 文件页数： | 10/16页 |
| 文件大小： | 795K |
| 代理商： | MPC9230FN |
MPC9230 REVISION 8 MARCH 29, 2010
3
2010 Integrated Device Technology, Inc.
MPC9230 Data Sheet
800MHZ LOW VOLTAGE PECL CLOCK SYNTHESIZER
Table 1. Pin Configurations
Pin
I/O
Default
Type
Function
XTAL_IN, XTAL_OUT
Analog
Crystal oscillator interface
FREF_EXT
Input
0
LVCMOS
Alternative PLL reference input
FOUT, FOUT
Output
LVPECL
Differential clock output
TEST
Output
LVPECL
Test and device diagnosis output
XTAL_SEL
Input
1
LVCMOS
PLL reference select input
S_LOAD
Input
0
LVCMOS
Serial configuration control input
This input controls the loading of the configuration latches with the contents of the shift register.
The latches will be transparent when this signal is high, thus the data must be stable on the
high-to-low transition.
P_LOAD
Input
1
LVCMOS
Parallel configuration control input.
This input controls the loading of the configuration latches with the content of the parallel inputs
(M and N). The latches will be transparent when this signal is low, thus the parallel data must
be stable on the low-to-high transition of P_LOAD. P_LOAD is state sensitive.
S_DATA
Input
0
LVCMOS
Serial configuration data input
S_CLOCK
Input
0
LVCMOS
Serial configuration clock input
M[0:8]
Input
1
LVCMOS
Parallel configuration for PLL feedback divider (M).
M is sampled on the low-to-high transition of P_LOAD
N[1:0]
Input
1
LVCMOS
Parallel configuration for Post-PLL divider (N).
N is sampled on the low-to-high transition of P_LOAD
OE
Input
1
LVCMOS
Output enable (active high)
The output enable is synchronous to the output clock to eliminate the possibility of runt pulses
on the FOUT output
GND
Supply
Ground
Negative power supply (GND)
VCC
Supply
VCC
Positive power supply for I/O and core. All VCC pins must be connected to the positive power
supply for correct operation
VCC_PLL
Supply
VCC
PLL positive power supply (analog power supply)
Table 2. Output Frequency Range and PLL Post-Divider N
N
Output Division
Output Frequency Range
for TA = 0°C to +70°C
Output Frequency Range
for TA = –40°C to +85°C
1
0
0
2
200 – 400 MHz
200 – 375 MHz
0
1
4
100 – 200 MHz
100 – 187.5 MHz
1
0
8
50 – 100 MHz
50 – 93.75 MHz
1
400 – 800 MHz
400 – 750 MHz
Table 3. Function Table
Input
0
1
XTAL_SEL
FREF_EXT
XTAL interface
OE
Outputs disabled. FOUT is stopped in the logic low state
(FOUT = L, FOUT = H)
Outputs enabled
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