- 您现在的位置：买卖IC网 > PDF目录53816 > MPC9230FNR2 (FREESCALE SEMICONDUCTOR INC) 800 MHz, OTHER CLOCK GENERATOR, PQCC28 PDF资料下载
参数资料
| 型号： | MPC9230FNR2 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 800 MHz, OTHER CLOCK GENERATOR, PQCC28 |
| 封装： | PLASTIC, LCC-28 |
| 文件页数： | 7/9页 |
| 文件大小： | 133K |
| 代理商： | MPC9230FNR2 |
4
MPC9230
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
414
Substituting N for the four available values for N (1, 2, 4, 8)
yields:
Table 9. Output Frequency Range for fXTAL = 16 MHz
N
FOUT
FOUT range
FOUT step
1
0
Value
OUT
g
OUT
p
0
2
M
200 - 400 MHz
1 MHz
0
1
4
M
÷2
100 - 200 MHz
500 kHz
1
0
8
M
÷4
50 - 100 MHz
250 kHz
1
2
M
400 - 800 MHz
2 MHz
Example frequency calculation for an 16 MHz input fre-
quency
If an output frequency of 131 MHz was desired the following
steps would be taken to identify the appropriate M and N values.
According to Table 9, 131 MHz falls in the frequency set by a
value of 4 so N[1:0] = 01. For N = 4 the output frequency is FOUT
= M
÷ 2 and M = FOUT x 2. Therefore M = 2 x 131 = 262, so M[8:0]
= 010000011. Following this procedure a user can generate any
whole frequency between 50 MHz and 800 MHz. Note than for
N > 2 fractional values of can be realized. The size of the
programmable frequency steps (and thus the indicator of the
fractional output frequencies achievable) will be equal to:
fSTEP = fXTAL ÷ 8 ÷ N
(6)
Using the parallel and serial interface
The M and N counters can be loaded either through a parallel
or serial interface. The parallel interface is controlled via the
P_LOAD signal such that a LOW to HIGH transition will latch the
information present on the M[8:0] and N[1:0] inputs into the M
and N counters. When the P_LOAD signal is LOW the input
latches will be transparent and any changes on the M[8:0] and
N[1:0] inputs will affect the FOUT output pair. To use the serial
port the S_CLOCK signal samples the information on the
S_DATA line and loads it into a 14 bit shift register. Note that the
P_LOAD signal must be HIGH for the serial load operation to
function. The Test register is loaded with the first three bits, the
N register with the next two and the M register with the final eight
bits of the data stream on the S_DATA input. For each register
the most significant bit is loaded first (T2, N1 and M8). A pulse
on the S_LOAD pin after the shift register is fully loaded will
transfer the divide values into the counters. The HIGH to LOW
transition on the S_LOAD input will latch the new divide values
into the counters. Figure 4 illustrates the timing diagram for both
a parallel and a serial load of the MPC9230 synthesizer. M[8:0]
and N[1:0] are normally specified once at power–up through the
parallel interface, and then possibly again through the serial
interface. This approach allows the application to come up at
one frequency and then change or fine–tune the clock as the
ability to control the serial interface becomes available.
Using the test and diagnosis output TEST
The TEST output provides visibility for one of the several
internal nodes as determined by the T[2:0] bits in the serial
configuration stream. It is not configurable through the parallel
interface. Although it is possible to select the node that
represents FOUT, the LVPECL compatible TEST output is not
able to toggle fast enough for higher output frequencies and
should only be used for test and diagnosis. The T2, T1 and T0
control bits are preset to ‘000’ when P_LOAD is LOW so that the
LVPECL compatible FOUT outputs are as jitter–free as
possible. Any active signal on the TEST output pin will have
detrimental affects on the jitter of the PECL output pair. In
normal operations, jitter specifications are only guaranteed if
the TEST output is static. The serial configuration port can be
used to select one of the alternate functions for this pin. Most of
the signals available on the TEST output pin are useful only for
performance verification of the MPC9230 itself. However the
PLL bypass mode may be of interest at the board level for
functional debug. When T[2:0] is set to 110 the MPC9230 is
placed in PLL bypass mode. In this mode the S_CLOCK input
is fed directly into the M and N dividers. The N divider drives the
FOUT differential pair and the M counter drives the TEST output
pin. In this mode the S_CLOCK input could be used for low
speed board level functional test or debug. Bypassing the PLL
and driving FOUT directly gives the user more control on the test
clocks sent through the clock tree. Table 10 shows the
functional setup of the PLL bypass mode. Because the
S_CLOCK is a CMOS level the input frequency is limited to 200
MHz. This means the fastest the FOUT pin can be toggled via the
S_CLOCK is 50 MHz as the divide ratio of the Post-PLL divider
is 4 (if N = 1). Note that the M counter output on the TEST output
will not be a 50% duty cycle.
Table 10. Test and Debug Configuration for TEST
T[2:0]
TEST output
T2
T1
T0
p
0
14-bit shift register outa
0
1
Logic 1
0
1
0
fXTAL ÷ 16
0
1
M-Counter out
1
0
FOUT
1
0
1
Logic 0
1
0
M-Counter out in PLL-bypass mode
1
FOUT
÷ 4
a. Clocked out at the rate of S_CLOCK
Table 11. Debug Configuration for PLL bypassa
Output
Configuration
FOUT
S_CLOCK
÷ N
TEST
M-Counter outb
a. T[2:0]=110. AC specifications do not apply in PLL bypass
mode
b. clocked out at the rate of S_CLOCK
÷(2N)
相关PDF资料 |
PDF描述 |
|---|---|
| MPC9230FN | 800 MHz, OTHER CLOCK GENERATOR, PQCC28 |
| MPC9230FAR2 | 800 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| MPC9230FAR2 | 800 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| MPC92430FA | 800 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| MPC9330FAR2 | 120 MHz, OTHER CLOCK GENERATOR, PQFP32 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC9239 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:900 MHz Low Voltage LVPECL Clock Synthesizer |
| MPC9239AC | 功能描述:时钟合成器/抖动清除器 2.5 3.3V 250MHz Clock Generator RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| MPC9239ACR2 | 功能描述:时钟合成器/抖动清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| MPC9239EI | 功能描述:时钟合成器/抖动清除器 FSL 900MHz LVPECL Freq. Synthesizer RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| MPC9239EIR2 | 功能描述:时钟合成器/抖动清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
发布紧急采购，3分钟左右您将得到回复。