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参数资料
| 型号： | MPC92433AER2 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 1428 MHz, OTHER CLOCK GENERATOR, PQFP48 |
| 封装： | ROHS COMPLIANT, LQFP-48 |
| 文件页数： | 15/20页 |
| 文件大小： | 412K |
| 代理商： | MPC92433AER2 |
Advanced Clock Drivers Devices
4
Freescale Semiconductor
MPC92433
Table 2. Function Table
Control
Default(1)
1. Default states are set by internal input pull-up or pull-down resistors of 75 k
.
01
Inputs
REF_SEL
1
Selects REF_CLK input as PLL reference clock
Selects the XTAL interface as PLL reference
clock
M[9:0]
01 1111 0100b(2)
2. If fREF = 16 MHz, the default configuration will result in an output frequency of 250 MHz.
PLL feedback divider (10-bit) parallel programming interface
NA[2:0]
010
PLL post-divider parallel programming interface. See Table 9
NB
0
PLL post-divider parallel programming interface. See Table 9
P
1
PLL pre-divider parallel programming interface. See Table 8
PLOAD
0
Selects the parallel programming interface. The
internal PLL divider settings (M, NA, NB and P) are
equal to the setting of the hardware pins. Leaving the
M, NA, NB and P pins open (floating) results in a
default PLL configuration with fOUT = 250 MHz. See
application/programming section.
Selects the serial (I2C) programming interface.
The internal PLL divider settings (M, NA, NB and
P) are set and read through the serial interface.
ADR[1:0]
00
Address bit = 0
Address bit = 1
SDA, SCL
See Programming the MPC92433
BYPASS
1
PLL function bypassed
fQA=fREF÷ NA and
fQB=fREF÷ (NA NB)
PLL function enabled
fQA = (fREF÷ P) M ÷ NA and
fQB = (fREF ÷ P) M ÷ (NA NB)
TEST_EN
0
Application mode. Test mode disabled.
Factory test mode is enabled
CLK_STOPx
1
Output Qx is disabled in logic low state. Synchronous
disable is only guaranteed if NB = 0.
Output Qx is synchronously enabled
MR
The device is reset. The output frequency is zero and
the outputs are asynchronously forced to logic low
state.
After releasing reset (upon the rising edge of MR and
independent on the state of PLOAD), the MPC92433
reads the parallel interface (M, NA, NB and P) to
acquire a valid startup frequency configuration. See
application/programming section.
The PLL attempts to lock to the reference signal.
The tLOCK specification applies.
Outputs
LOCK
PLL is not locked
PLL is frequency locked
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相关代理商/技术参数 |
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| MPC92439 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:900MHz, Low Voltage, LVPECL Clock Syntheesizer |
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| MPC92439ACR2 | 功能描述:IC SYNTHESIZER LVPECL 32-LQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
| MPC92439EI | 功能描述:时钟合成器/抖动清除器 FSL 900MHz LVPECL Freq. Synthesizer RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| MPC92439EIR2 | 功能描述:时钟合成器/抖动清除器 FSL 900MHz LVPECL Freq. Synthesizer RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
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