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| 型号： | MPC9352ACR2 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 1/16页 |
| 文件大小： | 0K |
| 描述： | IC CLK GEN ZD 1:11 32-LQFP |
| 标准包装： | 2,000 |
| 类型： | PLL 时钟发生器 |
| PLL： | 带旁路 |
| 输入： | LVCMOS |
| 输出： | LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:11 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 200MHz |
| 除法器/乘法器： | 是/是 |
| 电源电压： | 2.375 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-TQFP（7x7） |
| 包装： | 带卷 (TR) |
DATASHEET
3.3V/2.5V 1:11 LVCMOS Zero Delay
Clock Generator
MPC9352
NRND
MPC9352 REVISION 8 JANUARY 31, 2013
1
2013 Integrated Device Technology, Inc.
The MPC9352 is a 3.3 V or 2.5 V compatible, 1:11 PLL based clock generator
targeted for high performance clock tree applications. With output frequencies up
to 200 MHz and output skews lower than 200 ps, the device meets the needs of
most demanding clock applications.
Features
Configurable 11 Outputs LVCMOS PLL Clock Generator
Fully Integrated PLL
Wide Range of Output Clock Frequency of 16.67 MHz to 200 MHz
Multiplication of the Input Reference Clock Frequency by 3, 2, 1, 3
2, 2 3,
1
3 and 1 2
2.5 V and 3.3 V LVCMOS Compatible
Maximum Output Skew of 200 ps
Supports Zero-Delay Applications
Designed for High-Performance Telecom, Networking and Computing
Applications
32-Lead LQFP Package, Pb-Free
Ambient Temperature Range –40°C to +85°C
NRND – Not Recommend for New Designs
The MPC9352 is a fully 3.3 V or 2.5 V compatible PLL clock generator and clock driver. The device has the capability to gen-
erate output clock signals of 16.67 to 200 MHz from external clock sources. The internal PLL is optimized for its frequency range
and does not require external lock filter components. One output of the MPC9352 has to be connected to the PLL feedback input
FB_IN to close the external PLL feedback path. The output divider of this output setting determines the PLL frequency multipli-
cation factor. This multiplication factor, F_RANGE, and the reference clock frequency must be selected to situate the VCO in its
specified lock range. The frequency of the clock outputs can be configured individually for all three output banks by the FSELx
pins supporting systems with different, but phase-aligned, clock frequencies.
The PLL of the MPC9352 minimizes the propagation delay, and therefore, supports zero-delay applications. All inputs and out-
puts are LVCMOS compatible. The outputs are optimized to drive parallel terminated 50
transmission lines. Alternatively, each
output can drive up to two series terminated transmission lines giving the device an effective fanout of 22.
The device also supports output high-impedance disable and a PLL bypass mode for static system test and diagnosis. The
MPC9352 is packaged in a 32 ld LQFP.
MPC9352
LOW VOLTAGE
3.3 V/2.5 V LVCMOS 1:11
CLOCK GENERATOR
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-03
NRND – Not Recommend for New Designs
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| MPC9352FAR2 | 制造商:Integrated Device Technology Inc 功能描述:Zero Delay PLL Clock Generator Single 32-Pin LQFP T/R 制造商:Integrated Device Technology Inc 功能描述:ZERO DLY PLL CLOCK GEN SGL 32LQFP - Tape and Reel |
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| MPC93H51FA | 功能描述:IC PLL CLK DVR HI-DRIVE 32-LQFP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
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