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| 型号： | MPC93H52ACR2 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 11/14页 |
| 文件大小： | 0K |
| 描述： | IC CLK GEN ZD 1:11 32-LQFP |
| 标准包装： | 2,000 |
| 类型： | PLL 时钟发生器 |
| PLL： | 带旁路 |
| 输入： | LVCMOS |
| 输出： | LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:11 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 240MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-TQFP（7x7） |
| 包装： | 带卷 (TR) |
MPC93H52 REVISION 5 FEBRUARY 15, 2013
6
2013 Integrated Device Technology, Inc.
MPC93H52 Data Sheet
3.3 V 1:11 LVCMOS ZERO DELAY CLOCK GENERATOR
APPLICATIONS INFORMATION
Programming the MPC93H52
The MPC93H52 supports output clock frequencies from
16.67 to 240 MHz. Different feedback and output divider
configurations can be used to achieve the desired input to
output frequency relationship. The feedback frequency and
divider should be used to situate the VCO in the frequency
lock range between 200 and 480 MHz for stable and optimal
operation. The FSELA, FSELB, FSELC pins select the
desired output clock frequencies. Possible frequency ratios
of the reference clock input to the outputs are 1:1, 1:2, 1:3,
3:2 as well as 2:3, 3:1 and 2:1. Table 7 illustrates the various
output configurations and frequency ratios supported by the
MPC93H52. See also Table 8 and Figure 3 to Figure 6 for
further reference. A 2 output divider cannot be used for
feedback.
Table 7. MPC93H52 Example Configuration (F_RANGE = 0)
PLL
Feedback
fref(1)
[MHz]
1. fref is the input clock reference frequency (CCLK).
FSELA
FSELB
FSELC
QA[0:4]:fref ratio
QB[0:3]:fref ratio
QC[0:1]:fref ratio
VCO
4(2)
2. fref is the input clock reference frequency (CCLK).
50-120
0
fref
(50-120 MHz) fref
2
(100-240 MHz)
0
1
fref
(50-120 MHz) fref
(50-120 MHz)
1
0
fref
23
(33-80 MHz) fref
(50-120 MHz) fref
2
(100-240 MHz)
1
0
1
fref
23
(33-80 MHz) fref
(50-120 MHz) fref
(50-120 MHz)
VCO
6(3)
3. fref is the input clock reference frequency (CCLK).
33.3-80
1
0
fref
(33-80 MHz) fref
32
(50-120 MHz) fref
3
(100-240 MHz)
1
0
1
fref
(33-80 MHz) fref
32
(50-120 MHz) fref
32
(50-120 MHz)
1
0
fref
(33-80 MHz) fref
3
(100-240 MHz) fref
3
(100-240 MHz)
1
fref
(33-80 MHz) fref
3
(100-240 MHz) fref
32
(50-120 MHz)
Table 8. MPC93H52 Example Configurations (F_RANGE = 1)
PLL
Feedback
fref(1)
[MHz]
1. fref is the input clock reference frequency (CCLK).
FSELA
FSELB
FSELC
QA[0:4]:fref ratio
QB[0:3]:fref ratio
QC[0:1]:fref ratio
VCO
8(2)
2. QAx connected to FB_IN and FSELA=0.
25-60
0
fref
(25-60 MHz) fref
2
(50-120 MHz)
0
1
fref
(25-60 MHz) fref
(25-60 MHz)
100
fref
23
(16-40 MHz) fref
(25-60 MHz) fref
2
(50-120 MHz)
101
fref
23
(16-40 MHz) fref
(25-60 MHz) fref
(25-60 MHz)
VCO
12(3)
3. QAx connected to FB_IN and FSELA=1.
16.67-40
1
0
fref
(16-40 MHz) fref
32
(25-60 MHz) fref
3
(50-120 MHz)
1
0
1
fref
(16-40 MHz) fref
32
(25-60 MHz) fref
32
(25-60 MHz)
1
0
fref
(16-40 MHz) fref
3
(50-120 MHz) fref
3
(50-120 MHz)
1
fref
(16-40 MHz) fref
3
(50-120 MHz) fref
32
(25-60 MHz)
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