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| 型号： | MPC93R51AC |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 93R SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封装： | 7 X 7 MM, LEAD FREE, LQFP-32 |
| 文件页数： | 1/12页 |
| 文件大小： | 339K |
| 代理商： | MPC93R51AC |
MPC93R51
Rev. 4, 1/2005
Freescale Semiconductor
Technical Data
Freescale Confidential Proprietary, NDA Required / Preliminary
Freescale Semiconductor, Inc., 2005. All rights reserved.
This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
Low Voltage PLL Clock Driver
The MPC93R51 is a 3.3 V compatible, PLL based clock generator targeted for
high performance clock distribution systems. With output frequencies of up to
240 MHz and a maximum output skew of 150 ps, the MPC93R51 is an ideal
solution for the most demanding clock tree designs. The device offers 9 low skew
clock outputs, each is configurable to support the clocking needs of the various
high-performance microprocessors including the PowerQuicc II integrated
communication microprocessor. The devices employ a fully differential PLL
design to minimize cycle-to-cycle and long-term jitter.
Features
9 outputs LVCMOS PLL clock generator
25–240 MHz output frequency range
Fully integrated PLL
Compatible to various microprocessors such as PowerQuicc II
Supports networking, telecommunications and computer applications
Configurable outputs: divide-by-2, 4 and 8 of VCO frequency
LVPECL and LVCMOS compatible inputs
External feedback enables zero-delay configurations
Output enable/disable and static test mode (PLL enable/disable)
Low skew characteristics: maximum 150 ps output-to-output
Cycle-to-cycle jitter max. 22 ps RMS
32-lead LQFP package
32-lead Pb-free Package Available
Ambient Temperature Range 0°C to +70°C
Pin & Function Compatible with the MPC951
Functional Description
The MPC93R51 utilizes PLL technology to frequency and phase lock its outputs onto an input reference clock. Normal
operation of the MPC93R51 requires a connection of one of the device outputs to the EXT_FB input to close the PLL feedback
path. The reference clock frequency and the output divider for the feedback path determine the VCO frequency. Both must be
selected to match the VCO frequency range. With available output dividers of divide-by-4 and divide-by-8, the internal VCO of
the MPC93R51 is running at either 4x or 8x of the reference clock frequency. The frequency of the QA, QB, QC and QD outputs
is either the one half, one fourth or one eighth of the selected VCO frequency and can be configured for each output bank using
the FSELA, FSELB, FSELC and FSELD pins, respectively. The available output to input frequency ratios are 4:1, 2:1, 1:1, 1:2
and 1:4. The REF_SEL pin selects the differential LVPECL (PCLK and PCLK) or the LVCMOS compatible reference input
(TCLK). The MPC93R51 also provides a static test mode when the PLL enable pin (PLL_EN) is pulled to logic low state. In test
mode, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The test mode is intended
for system diagnostics, test and debug purposes. This test mode is fully static and the minimum clock frequency specification
does not apply. The outputs can be disabled by deasserting the OE pin (logic high state). In PLL mode, deasserting OE causes
the PLL to loose lock due to no feedback signal presence at EXT_FB. Asserting OE will enable the outputs and close the phase
locked loop, also enabling the PLL to recover to normal operation. The MPC93R51 is 3.3 V compatible and requires no external
loop filter components. All inputs except PCLK and PCLK accept LVCMOS signals while the outputs provide LVCMOS compatible
levels with the capability to drive terminated 50
transmission lines. For series terminated transmission lines, each of the
MPC93R51 outputs can drive one or two traces giving the devices an effective fanout of 1:18. The device is packaged in a
7x7 mm2 32-lead LQFP package.
Application Information
The fully integrated PLL of the MPC93R51 allows the low skew outputs to lock onto a clock input and distribute it with
essentially zero propagation delay to multiple components on the board. In zero-delay buffer mode, the PLL minimizes phase
offset between the outputs and the reference signal.
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-03
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-03
MPC93R51
LOW VOLTAGE 3.3 V
PLL CLOCK GENERATOR
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相关代理商/技术参数 |
参数描述 |
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| MPC93R51ACR2 | 功能描述:时钟发生器及支持产品 FSL 1-9 LVCMOS/LVPEC L to LVCMOS PLL Cloc RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC93R51D | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC93R51FA | 功能描述:时钟驱动器及分配 3.3V 240MHz Clock Generator RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
| MPC93R51FAR2 | 制造商:Integrated Device Technology Inc 功能描述:PLL CLOCK DRVR SGL 32LQFP - Tape and Reel |
| MPC93R52 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:LOW VOLTAGE 3.3V LVCMOS 1:11 CLOCK GENERATOR |
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