参数资料
型号: MPC93R52ACR2
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟及定时
英文描述: 93R SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封装: LEAD FREE, LQFP-32
文件页数: 1/16页
文件大小: 337K
代理商: MPC93R52ACR2
MPC93R52
Rev. 5, 1/2005
Freescale Semiconductor
Technical Data
Freescale Semiconductor, Inc., 2005. All rights reserved.
This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
3.3 V 1:11 LVCMOS Zero Delay
Clock Generator
The MPC93R52 is a 3.3 V compatible, 1:11 PLL based clock generator
targeted for high performance clock tree applications. With output frequencies up
to 240 MHz and output skews lower than 200 ps, the device meets the needs of
most demanding clock applications.
Features
Configurable 11 outputs LVCMOS PLL clock generator
Fully integrated PLL
Wide range of output clock frequency of 16.67 MHz to 240 MHz
Multiplication of the input reference clock frequency by 3, 2, 1, 3
÷ 2, 2 ÷ 3,
1
÷ 3, and 1 ÷ 2
3.3 V LVCMOS compatible
Maximum output skew of 200 ps
Supports zero-delay applications
Designed for high-performance telecom, networking and computing
applications
32-lead LQFP package
32-lead Pb-free package available
Ambient Temperature Range – 0°C to +70°C
Pin and function compatible to the MPC952
Functional Description
The MPC93R52 is a fully 3.3 V compatible PLL clock generator and clock driver. The device has the capability to generate
output clock signals of 16.67 to 240 MHz from external clock sources. The internal PLL is optimized for its frequency range and
does not require external look filter components. One output of the MPC93R52 has to be connected to the PLL feedback input
FB_IN to close the external PLL feedback path. The output divider of this output setting determines the PLL frequency multipli-
cation factor. This multiplication factor, F_RANGE and the reference clock frequency must be selected to situate the VCO in its
specified lock range. The frequency of the clock outputs can be configured individually for all three output banks by the FSELx
pins supporting systems with different but phase-aligned clock frequencies.
The PLL of the MPC93R52 minimizes the propagation delay and therefore supports zero-delay applications. All inputs and
outputs are LVCMOS compatible. The outputs are optimized to drive parallel terminated 50
transmission lines. Alternatively,
each output can drive up to two series terminated transmission lines giving the device an effective fanout of 22.
The device also supports output high-impedance disable and a PLL bypass mode for static system test and diagnosis. The
MPC93R52 is package in a 32 ld LQFP.
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-03
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-03
MPC93R52
LOW VOLTAGE
3.3 V LVCMOS 1:11
CLOCK GENERATOR
相关PDF资料
PDF描述
MPC93R52AC 93R SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
MPC940FA MPC900 SERIES, LOW SKEW CLOCK DRIVER, 18 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
MPC940LAC 940 SERIES, LOW SKEW CLOCK DRIVER, 18 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
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