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参数资料
| 型号： | MPC940LFA |
| 厂商： | MOTOROLA INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | MPC900 SERIES, LOW SKEW CLOCK DRIVER, 18 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封装： | 7 X 7 MM, LQFP-32 |
| 文件页数： | 5/6页 |
| 文件大小： | 106K |
| 代理商： | MPC940LFA |
6
MPC940L
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
537
DC CHARACTERISTICS (TA = 0° to 70°C, VCCI = 2.5V ±5%; VCCO = 2.5V ±5%)
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
VIH
Input HIGH Voltage
CMOS_CLK
2.0
VCCI
V
VIL
Input LOW Voltage
CMOS_CLK
0.8
V
VPP
Peak–to–Peak Input Voltage
PECL_CLK
500
1000
mV
VCMR
Common Mode Range
PECL_CLK
VCC–1.0
VCC–0.6
V
VOH
Output HIGH Voltage
1.8
V
IOH = –12mA
VOL
Output LOW Voltage
0.5
V
IOH = 12mA
IIN
Input Current
±200
A
CIN
Input Capacitance
4.0
pF
Cpd
Power Dissipation Capacitance
10
pF
per output
ZOUT
Output Impedance
18
23
28
W
ICC
Maximum Quiescent Supply Current
0.5
1.0
mA
AC CHARACTERISTICS (TA = 0° to 70°C, VCCI = 2.5V ±5%; VCCO = 2.5V ±5%)
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
Fmax
Maximum Input Frequency
200
MHz
tPLH
Propagation Delay
PECL_CLK
≤ 150MHz
CMOS_CLK
≤ 150MHz
2.6
2.3
4.0
3.1
5.2
4.0
ns
Note 1.
tPLH
Propagation Delay
PECL_CLK > 150MHz
CMOS_CLK > 150MHz
2.8
2.3
3.8
3.1
5.0
4.0
ns
tsk(o)
Output–to–Output Skew
PECL_CLK
CMOS_CLK
200
ps
Note 1.
tsk(pp)
Part–to–Part Skew
PECL_CLK < 150MHz
CMOS_CLK < 150MHz
2.6
1.7
ns
Notes 1., 2.
tsk(pp)
Part–to–Part Skew
PECL_CLK > 150MHz
CMOS_CLK > 150MHz
2.2
1.7
ns
Notes 1., 2.
tsk(pp)
Part–to–Part Skew
PECL_CLK
CMOS_CLK
1.2
1.0
ns
Notes 1., 3.
DC
Output Duty Cycle
fCLK < 134 MHz
fCLK ≤ 250 MHz
45
40
50
55
60
%
Input DC = 50%
tr, tf
Output Rise/Fall Time
0.3
1.2
ns
0.5 – 1.8 V
1. Tested using standard input levels, Production tested @ 150MHz.
2. Across temperature and voltage ranges, Includes output skew.
3. For a specific temperature and voltage, Includes output skew.
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