参数资料
型号: MPC9443AE
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 时钟及定时
英文描述: 9443 SERIES, LOW SKEW CLOCK DRIVER, 16 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48
封装: 7 X 7 MM, PLASTIC, LQFP-48
文件页数: 10/12页
文件大小: 209K
代理商: MPC9443AE
MPC9443
598
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
Table 11. DC Characteristics (VCC = 3.3 V ± 5%, any VCCA,B,C,D = 2.5 V ± 5% or 3.3 V ± 5% (mixed), TA = –40 to +85°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
VIH
Input High Voltage
2.0
VCC + 0.3
V
LVCMOS
VIL
Input Low Voltage
–0.3
0.8
V
LVCMOS
IIN
Input Current1
1.
Input pull-up / pull-down resistors influence input current.
200
A
VOH
Output High Voltage
2.5 V output
3.3 V output
1.7
2.0
V
IOH = –15 mA
2
IOH = 24 mA
2
2.
The MPC9443 is capable of driving 50
transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission
line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines (for VCC = 3.3 V) or one
50
series terminated transmission line (for V
CC =2.5 V).
VOL
Output Low Voltage
2.5 V output
3.3 V output
0.6
0.55
V
IOL = 15 mA
2
IOL = 24 mA
2
VPP
Peak-to-Peak Input Voltage
PCLK0,1
250
mV
LVPECL
VCMR
3
3.
VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the
input swing lies within the VPP (DC) specification.
Common Mode Range
PCLK0, 1
1.1
VCC – 0.6
V
LVPECL
ZOUT
Output Impedance
2.5 V output
3.3 V output
22
19
CPD
Power Dissipation Capacitance
10
pF
Per Output
ICCQ
4
4.
ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.
Maximum Quiescent Supply Current
3.0
mA
All VCC Pins
Table 12. AC Characteristics (VCC = 3.3 V ± 5%, any VCCA,B,C,D = 2.5 V ± 5% or 3.3 V ± 5% (mixed), TA = –40 to +85°C)
1 2
1.
AC characteristics apply for parallel output termination of 50
to V
TT.
2.
This table only specifies AC parameter in mixed voltage supply conditions that vary from the corresponding AC tables. For all other parameters,
see Table 8 (for 3.3 V outputs) or Table 10 (for 2.5 V outputs)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
tsk(LH, HL) Output-to-Output Skew3
Any output, same output divider
Any output, any output divider
3.
tsk(LH, HL) includes both device skew referenced to the rising output edge and device skew referenced to the falling output edge.
275
350
ps
tsk(PP)
Device-to-Device Skew
See Table 8 (3.3 V AC Characteristics)
tPLH, HL
Propagation Delay
See Table 8 (3.3 V AC Characteristics)
tSK(P)
DCQ
Output Pulse Skew4
Using PCLK0,1
Using CCLK
Output Duty Cycle
fQ<140 MHz and using CCLK
fQ<250 MHz and using PCLK0,1
4.
Output pulse skew is the absolute difference of the propagation delay times: | tPLH – tPHL |
45
50
400
500
55
ps
%
DCREF = 50%
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