参数资料
型号: MPC9448AC
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟及定时
英文描述: 9448 SERIES, LOW SKEW CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封装: LEAD FREE, LQFP-32
文件页数: 2/12页
文件大小: 486K
代理商: MPC9448AC
IDT / ICS LVCMOS 1:12 CLOCK FANOUT BUFFER
10
MPC9448
REV 6 JULY 11, 2006
MPC9448
3.3V/2.5V LVCMOS 1:12 CLOCK FANOUT BUFFER
Figure 13. Propagation Delay (tPD) Test Reference
Figure 14. Propagation Delay (tPD) Test Reference
Figure 15. Output-to-Output Skew tSK(LH, HL)
Figure 16. Output Pulse Skew (tSK(P)) Test Reference
Figure 17. Output Duty Cycle (DC)
Figure 18. Output Transition Time Test Reference
Figure 19. Cycle-to-Cycle Jitter
Figure 20. Setup and Hold Time (tS, tH) Test Reference
VCC
GND
PCLK
QX
PCLK
VPP
tP(LH)
tP(HL)
VCC
VCC÷2
GND
VCC
VCC÷2
GND
CCLK
QX
tP(LH)
tP(HL)
The pin-to-pin skew is defined as the worst case differ-
ence in propagation delay between any similar delay
path within a single device.
VCC
VCC÷2
GND
VCC
VCC÷2
GND
tSK(LH)
tSK(HL)
VCC
VCC÷2
GND
VCC
VCC÷2
GND
tP(LH)
CCLK
QX
tP(HL)
tSK(P) = | tPLH – tPHL |
The time from the output controlled edge to the non-
controlled edge, divided by the time between output
controlled edges, expressed as a percentage.
VCC
VCC÷2
GND
tP
T0
DC = (tP ? T0 x 100%)
tF
tR
VCC=3.3 V VCC=2.5 V
2.4
1.8 V
0.55
0.6 V
The variation in cycle time of a signal between ad-
jacent cycles, over a random sample of adjacent
cycle pairs.
TN
TJIT(CC) = |TN-TN+1|
TN+1
VCC
VCC÷2
GND
VCC
VCC÷2
GND
tS
CCLK
PCLK
CLK_STOP
tH
MPC9448
3.3 V/2.5 V LVCMOS 1:12 Clock Fanout Buffer
NETCOM
IDT 3.3 V/2.5 V LVCMOS 1:12 Clock Fanout Buffer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9448
10
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