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参数资料
| 型号： | MPC949FAR2 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 949 SERIES, LOW SKEW CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封装： | 10 X 10 MM, 0.65 MM PITCH, PLASTIC, LQFP-52 |
| 文件页数： | 3/4页 |
| 文件大小： | 272K |
| 代理商： | MPC949FAR2 |
6
MPC949
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
621
ABSOLUTE MAXIMUM RATINGS*
Symbol
Parameter
Min
Max
Unit
VCC
Supply Voltage
–0.3
4.6
V
VI
Input Voltage
–0.3
VDD + 0.3
V
IIN
Input Current
TBD
mA
TStor
Storage Temperature Range
–40
125
°C
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those
indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not implied.
DC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±5%)
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
VIH
Input HIGH Voltage
(Except PECL_CLK)
2.0
3.60
V
VIL
Input LOW Voltage
(Except PECL_CLK)
0.8
V
VPP
Peak–to–Peak Input Voltage
PECL_CLK
300
1000
mV
VCMR
Common Mode Range
PECL_CLK
VCC – 2.0
VCC – 0.6
V
Note 1.
VOH
Output HIGH Voltage
2.5
V
IOH = –20mA (Note 2.)
VOL
Output LOW Voltage
0.4
V
IOL = 20mA (Note 2.)
IIN
Input Current
±120
A
Note 3.
CIN
Input Capacitance
4
pF
Cpd
Power Dissipation Capacitance
25
pF
Per Output
ICC
Maximum Quiescent Supply Current
70
85
mA
1. VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “HIGH” input is within
the VCMR range and the input swing lies within the VPP specification.
2. The MPC949 can drive 50
transmission lines on the incident edge. Each output can drive one 50 parallel terminated transmission line to
the termination voltage of VTT = VCC/2. Alternately, the device drives up to two 50 series terminated transmission lines.
3. Inputs have pull–up/pull–down resistors which affect input current.
AC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±5%)
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
Fmax
Maximum Input Frequency
160
MHz
Note 4.
tPLH
Propagation Delay
PECL_CLK to Q
TTL_CLK to Q
4.0
4.2
6.5
7.5
9.0
10.6
ns
Note 4.
tPHL
Propagation Delay
PECL_CLK to Q
TTL_CLK to Q
3.8
4.0
6.2
7.2
8.6
10.5
ns
Note 4.
tsk(o)
Output–to–Output Skew
300
350
ps
Note 4.
tsk(pp)
Part–to–Part Skew
PECL_CLK to Q
TTL_CLK to Q
1.5
2.0
2.75
4.0
ns
Note 5.
tPZL,tPZH
Output Enable Time
3
11
ns
Note 4.
tPLZ,tPHZ
Output Disable Time
3
11
ns
Note 4.
tr, tf
Output Rise/Fall Time
0.10
1.0
ns
0.8V to 2.0V
4. Driving 50
transmission lines terminated to VCC/2.
5. Part–to–part skew at a given temperature and voltage.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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