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参数资料
| 型号： | MPC952FAR2 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | LVCMOS/LVTTL SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封装： | PLASTIC, LQFP-32 |
| 文件页数： | 3/6页 |
| 文件大小： | 97K |
| 代理商： | MPC952FAR2 |
MPC952
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
170
ABSOLUTE MAXIMUM RATINGS*
Symbol
Parameter
Min
Max
Unit
VCC
Supply Voltage
–0.3
4.6
V
VI
Input Voltage
–0.3
VCC + 0.3
V
IIN
Input Current
±20
mA
TStor
Storage Temperature Range
–40
125
°C
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or condi-
tions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not im-
plied.
THERMAL CHARACTERISTICS
Proper thermal management is critical for reliable system operation. This is especially true for high fanout and high drive capa-
bility products. Generic thermal information is available for the Motorola Clock Driver products. The means of calculating die
power, the corresponding die temperature and the relationship to longterm reliability is addressed in the Motorola application
note AN1545.
DC CHARACTERISTICS (TA = 0° to 70°C, VCCO = VCCI = VCCA = 3.3V ±5%)
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
VIH
Input HIGH Voltage
2.0
3.6
V
VIL
Input LOW Voltage
0.8
V
VOH
Output HIGH Voltage
2.4
V
IOH = –20mA (Note 1.)
VOL
Output LOW Voltage
0.5
V
IOL = 20mA (Note 1.)
IIN
Input Current
±120
A
Note 2.
CIN
Input Capacitance
2.7
4.0
pF
Cpd
Power Dissipation Capacitance
25
pF
ICC
Maximum Quiescent Supply Current
160
mA
Total ICC Static Current
ICCA
PLL Supply Current
15
20
mA
1. The MPC952 outputs can drive series or parallel terminated 50
(or 50 to VCCO/2) transmission lines on the incident edge (see Applications
Info section).
2. Inputs have pull–up, pull–down resistors which affect input current.
PLL INPUT REFERENCE CHARACTERISTICS (TA = 0 to 70°C)
Symbol
Characteristic
Min
Max
Unit
Condition
tr, tf
TCLK Input Rise/Falls
3.0
ns
fref
Reference Input Frequency
100
MHz
Note 3.
frefDC
Reference Input Duty Cycle
25
75
%
3. Maximum and minimum input reference is limited by the VCO lock range and the feedback divider.
2
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