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| 型号： | MPC961PACR2 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 961 SERIES, PLL BASED CLOCK DRIVER, 17 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封装： | PLASTIC, LQFP-32 |
| 文件页数： | 2/10页 |
| 文件大小： | 348K |
| 代理商： | MPC961PACR2 |
5
MPC961P
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
495
Figure 12. Propagation delay (t(), static phase
offset) test reference
Figure 13. Output Transition Time Test Reference
Figure 14. Output Duty Cycle (DC)
Figure 15. Output–to–output Skew tSK(O)
The pin-to-pin skew is defined as the worst case difference in propa
gation delay between any similar delay path within a single device
The time from the PLL controlled edge to the non controlled edge, divided
by the time between PLL controlled edges, expressed as a percentage
VCC
VCCB2
GND
VCC
VCCB2
GND
tSK(O)
VCC
VCCB2
GND
tP
T0
DC = tP/T0 x 100%
VCC
VCCB2
GND
t()
PCLK
Ext_FB
PCLK
tF
tR
VCC=3.3V
VCC=2.5V
2.4
1.8V
0.55
0.6V
VCMR
VPP
Figure 16. Cycle–to–cycle Jitter
Figure 17. Period Jitter
The variation in cycle time of a signal between adjacent cycles, over a
random sample of adjacent cycle pairs
The deviation in cycle time of a signal with respect to the ideal period over
a random sample of cycles
TN
TJIT(CC) = |TN-TN+1|
TN+1
TJIT(PER) = |TN-1/f0|
T0
Figure 18. I/O Jitter
TJIT() = |T0-T1mean|
PCLK
Ext_FB
The deviation in t0 for a controlled edge with respect to a t0 mean in a
random sample of cycles
PCLK
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For More Information On This Product,
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| MPC961PFAR2 | 961 SERIES, PLL BASED CLOCK DRIVER, 17 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
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| MPC962305D-1HR2 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:Low-Cost 3.3 V Zero Delay Buffer |
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