- 您现在的位置：买卖IC网 > PDF目录26839 > MPC962305DT-1H (INTEGRATED DEVICE TECHNOLOGY INC) 962305 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 PDF资料下载
参数资料
| 型号： | MPC962305DT-1H |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 962305 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封装： | 0.150 INCH, PLASTIC, TSSOP-8 |
| 文件页数： | 1/17页 |
| 文件大小： | 525K |
| 代理商： | MPC962305DT-1H |
LOW-COST, 3.3V ZERO DELAY BUFFER
MPC962305
IDT / ICS 3.3V ZERO DELAY BUFFER
1
MPC962305 REV 7 JULY 16, 2007
The MPC962309 is a zero delay buffer designed to distribute high-speed
clocks. Available in a 16-pin SOIC or TSSOP package, the device accepts one
reference input and drives nine low-skew clocks. The MPC962305 is the 8-pin
version of the MPC962309 which drives five outputs with one reference input.
The -1H versions of these devices have higher drive than the -1 devices and can
operate up to 100/-133 MHz frequencies. These parts have on-chip PLLs which
lock to an input clock presented on the REF pin. The PLL feedback is on-chip and
is obtained from the CLOCKOUT pad.
Features
1:5 LVCMOS zero-delay buffer (MPC962305)
1:9 LVCMOS zero-delay buffer (MPC962309)
Zero input-output propagation delay
Multiple low-skew outputs
250 ps max output-output skew
700 ps max device-device skew
Supports a clock I/O frequency range of 10 MHz to 133 MHz,
compatible with CPU and PCI bus frequencies
Low jitter, 200 ps max cycle-cycle, and compatible with Pentium based
systems
Test Mode to bypass PLL (MPC962309 only. See Table 3)
8-pin SOIC or 8-pin TSSOP package (MPC962305);16-pin SOIC or 16-pin
TSSOP package (MPC962309)
Single 3.3 V supply
Ambient temperature range: –40
°C to +85°C
Compatible with the CY2305, CY23S05, CY2309, CY23S09
Spread spectrum compatible
Pb-free packages available
Functional Description
The MPC962309 has two banks of four outputs each, which can be controlled
by the Select Inputs as shown in Table 3. Bank B can be tri-stated if all of the
outputs are not required. Select inputs also allow the input clock to be directly
applied to the outputs for chip and system testing purposes.
The MPC962305 and MPC962309 PLLs enters a power down state when
there are no rising edges on the REF input. During this state, all of the outputs
are in tristate, the PLL is turned off, and there is less than 25.0
A of current draw
for the device. The PLL shuts down in one additional case as shown in Table 3.
Multiple MPC962305 and MPC962309 devices can accept the same input
clock and distribute it throughout the system. In this situation, the difference between the output skews of two devices will be less
than 700 ps.
All outputs have less than 200 ps of cycle-cycle jitter. The input-to-output propagation delay on both devices is guaranteed to
be less than 350 ps and the output-to-output skew is guaranteed to be less than 250 ps.
The MPC962305 and MPC962309 are available in two/three different configurations, as shown on the ordering information
page. The MPC962305-1/MPC962309-1 are the base parts. High drive versions of those devices, MPC962305-1H and
MPC962309-1H, are available to provide faster rise and fall times of the base device.
Pentium II is a trademark of Intel Corporation.
MPC962305
MPC962309
D SUFFIX
16-LEAD SOIC PACKAGE
CASE 751B-05
D SUFFIX
8-LEAD SOIC PACKAGE
CASE 751-06
DT SUFFIX
8-LEAD TSSOP PACKAGE
CASE 948J-01
EF SUFFIX
8-LEAD SOIC PACKAGE
Pb-FREE PACKAGE
CASE 751-06
EJ SUFFIX
8-LEAD TSSOP PACKAGE
Pb-FREE PACKAGE
CASE 948J-01
EF SUFFIX
16-LEAD SOIC PACKAGE
Pb-FREE PACKAGE
CASE 751B-05
DT SUFFIX
16-LEAD TSSOP PACKAGE
CASE 948F-01
EJ SUFFIX
16-LEAD TSSOP PACKAGE
Pb-FREE PACKAGE
CASE 948F-01
相关PDF资料 |
PDF描述 |
|---|---|
| MPC9653AACR2 | 9653 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MPC9653AFA | 9653 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MPC9653AAC | 9653 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MPC9653FA | 9653 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MPC9658FA | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC962305DT-1HR2 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:Low-Cost 3.3 V Zero Delay Buffer |
| MPC962305EF-1 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:Low-Cost, 3.3V Zero Delay Buffer |
| MPC962305EF-1H | 功能描述:时钟缓冲器 RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| MPC962305EF-1HR2 | 功能描述:时钟缓冲器 RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| MPC962305EF-1R2 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:Low-Cost, 3.3V Zero Delay Buffer |
发布紧急采购，3分钟左右您将得到回复。