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参数资料
| 型号： | MPC9855VMR2 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PBGA100 |
| 封装： | 11 X 11 MM, 1 MM PITCH, LEAD FREE, MAPBGA-100 |
| 文件页数： | 10/12页 |
| 文件大小： | 260K |
| 代理商： | MPC9855VMR2 |
Advanced Clock Drivers Devices
Freescale Semiconductor
7
MPC9855
Table 7. LVPECL DC Characteristics (TA = –40°C to 85°C)(1)
1. AC characteristics are design targets and pending characterization.
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
Differential LVPECL Clock Inputs (CLK1, CLK1) for VDD = 3.3 V ± 0.5%
VPP
Differential Voltage(2) (peak-to-peak)
(LVPECL)
2. VPP is the minimum differential input voltage swing required to maintain AC characteristics including tPD and device-to-device skew.
250
mV
VCMR
Differential Input Crosspoint Voltage(3)
(LVPECL)
3. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC)
range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay,
device and part-to-part skew.
1.0
VDD – 0.6
V
Table 8. LVCMOS I/O DC Characteristics (TA = –40°C to 85°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
LVCMOS for VDD = 3.3 V ± 5%
VIH
Input High Voltage
2.0
VDD + 0.3
V
LVCMOS
VIL
Input Low Voltage
0.8
V
LVCMOS
IIN
Input Current(1)
1. Inputs have pull-down resistors affecting the input current.
± 200
AVIN = VDDL or GND
LVCMOS for VDD = 3.3 V ± 5%, VDDOA = 3.3 V ± 5 and VDDOB = 3.3 V ± 5%
VOH
Output High Voltage
2.4
V
IOH = –24 mA
VOL
Output Low Voltage
0.5
V
IOL = 24 mA
ZOUT
Output Impedance
14 – 17
LVCMOS for VDD= 3.3 V ± 5%, VDDOA = 2.5 V ± 5% and VDDOB= 2.5 V ± 5%
VOH
Output High Voltage
1.9
V
IOH = –15 mA
VOL
Output Low Voltage
0.4
V
IOL = 15 mA
ZOUT
Output Impedance
18 – 22
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