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参数资料
型号： MPC991FAR2
厂商： INTEGRATED DEVICE TECHNOLOGY INC
元件分类： 时钟及定时
英文描述： PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52
封装： TQFP-52
文件页数： 5/9页
文件大小： 147K
代理商： MPC991FAR2
MPC990 MPC991
TIMING SOLUTIONS
BR1333 — Rev 6
5
MOTOROLA
ECL DC CHARACTERISTICS (TA = 0° to 70°C, VCCA = VCCI = VCCO = 0V, GNDI = –3.3V ±5%, Note 1.)
0
°C
25
°C
70
°C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
VOH
Output HIGH Voltage
–1.3
–0.7
–1.3
–1.0
–0.7
–1.3
–0.7
V
VOL
Output LOW Voltage
–2.0
–1.4
–2.0
–1.7
–1.4
–2.0
–1.4
V
VIH
Input HIGH Voltage
–1.1
–0.9
–1.1
–0.9
–1.1
–0.9
V
VIL
Input LOW Voltage
–1.8
–1.5
–1.8
–1.5
–1.8
–1.5
V
VPP
Minimum Input Swing
500
mV
VCMR
Common Mode Range
VCC
–1.3V
VCC
–0.5V
VCC
–1.3V
VCC
–0.5V
VCC
–1.3V
VCC
–0.5V
V
IIH
Input HIGH Current
150
A
IGNDI
Power Supply Current
200
240
200
240
200
240
mA
1. Refer to Motorola Application Note AN1545/D “
Thermal Data for MPC Clock Drivers” for thermal management guidelines.
PECL DC CHARACTERISTICS (TA = 0° to 70°C, VCCA = VCCI = VCCO = 3.3V ±5%, GNDI = 0V, Note 2.)
0
°C
25
°C
70
°C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
VOH
Output HIGH Voltage (Note 3.)
2.0
2.6
2.0
2.3
2.6
2.3
2.6
V
VOL
Output LOW Voltage (Note 3.)
1.3
1.9
1.3
1.6
1.9
1.3
1.9
V
VIH
Input HIGH Voltage (Note 3.)
2.2
2.4
2.2
2.4
2.2
2.4
V
VIL
Input LOW Voltage (Note 3.)
1.5
1.8
1.5
1.8
1.5
1.8
V
VPP
Minimum Input Swing
500
mV
VCMR
Common Mode Range
VCC
–1.3V
VCC
–0.5V
VCC
–1.3V
VCC
–0.5V
VCC
–1.3V
VCC
–0.5V
V
IIH
Input HIGH Current
150
A
IGNDI
Power Supply Current
200
240
200
240
200
240
mA
2. Refer to Motorola Application Note AN1545/D “
Thermal Data for MPC Clock Drivers” for thermal management guidelines.
3. These values are for VCC = 3.3V. Level Specifications will vary 1:1 with VCC.
AC CHARACTERISTICS (TA = 0° to 70°C, VCCA = VCCI = VCCO = 3.3V ±5%, Termination of 50 to VCC – 2.0V)
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
fxtal
Crystal Oscillator Frequency
10
25
MHz
tr, tf
Output Rise/Fall Time
0.2
1.0
ns
20% to 80%
tpw
Output Duty Cycle
47.5
50
52.5
%
tos
Output-to-Output Skew
Same Frequency
Different Frequencies
150
250
350
ps
fVCO
PLL VCO Lock Range
VCO_Sel = ‘0’
VCO_Sel = ‘1’
400
200
800
400
MHz
FB
÷8 to ÷32 (Note 4.)
FB
÷4 to ÷32
tpd
Ref to Feedback Offset
75
250
425
ps
fref = 50MHz (Note 5.)
fmax
Maximum Output Frequency
Qa,Qb,Qc (
÷2)
Qa,Qb,Qc (
÷4)
Qa,Qb,Qc (
÷6)
Qa,Qb,Qc (
÷8)
400
200
133
100
MHz
tjitter
Cycle–to–Cycle Jitter (Peak–to–Peak)
±50
ps
tlock
Maximum PLL Lock Time
10
ms
4. With VCO_Sel = ‘0’, the PLL will be unstable with a
÷2, ÷4 and some ÷6 feedback configurations. With VCO_Sel = ‘1’, the PLL will be unstable
with a
÷2 feedback ratio.
5. tpd is specified for 50MHz input reference FB ÷8. The window will shrink/grow proportionally from the minimum limit with shorter/longer input
reference periods. The tpd does not include jitter.
相关PDF资料
PDF描述
MPC991FAR2 PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52
MPC993FA 993 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
MPC9952FAR2 PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
MPC9952FA PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
MPC9993ACR2 9993 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
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