参数资料
型号: MPC9993AC
厂商: IDT, Integrated Device Technology Inc
文件页数: 4/11页
文件大小: 0K
描述: IC PLL CLK DRIVER IDCS 32-LQFP
标准包装: 250
类型: PLL 时钟驱动器,动态时钟开关
PLL: 带旁路
输入: LVPECL
输出: LVPECL
电路数: 1
比率 - 输入:输出: 2:5
差分 - 输入:输出: 是/是
频率 - 最大: 200MHz
除法器/乘法器: 是/无
电源电压: 3.135 V ~ 3.465 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-LQFP
供应商设备封装: 32-TQFP(7x7)
包装: 托盘
MPC9993 REVISION 3 JANUARY 23, 2013
2
2013 Integrated Device Technology, Inc.
MPC9993 Data Sheet
INTELLIGENT DYNAMIC CLOCK SWITCH (IDCS) PLL CLOCK DRIVER
Figure 2. 32-Lead Pinout (Top View)
Table 1. Pin Descriptions
Pin Name
I/O
Pin Definition
CLK0, CLK0
CLK1, CLK1
LVPECL Input
Differential PLL clock reference (CLK0 pulldown, CLK0 pullup)
Differential PLL clock reference (CLK1 pulldown, CLK1 pullup)
Ext_FB, Ext_FB
LVPECL Input
Differential PLL feedback clock (Ext_FB pulldown, Ext_FB pullup)
Qa0:1, Qa0:1
LVPECL Output
Differential 1x output pairs
Qb0:2, Qb0:2
LVPECL Output
Differential 2x output pairs
Inp0bad
LVCMOS Output Indicates detection of a bad input reference clock 0 with respect to the feedback signal. The output is
active HIGH and will remain HIGH until the alarm reset is asserted
Inp1bad
LVCMOS Output Indicates detection of a bad input reference clock 1 with respect to the feedback signal. The output is
active HIGH and will remain HIGH until the alarm reset is asserted
Clk_Selected
LVCMOS Output ‘0' if clock 0 is selected, ‘1' if clock 1 is selected
Alarm_Reset
LVCMOS Input
‘0' will reset the input bad flags and align Clk_Selected with Sel_Clk. The input is “one-shotted”
(50 k
pullup)
Sel_Clk
LVCMOS Input
‘0' selects CLK0, ‘1' selects CLK1 (50 k
pulldown)
Manual_Override
LVCMOS Input
‘1' disables internal clock switch circuitry (50 k
pulldown)
PLL_En
LVCMOS Input
‘0' bypasses selected input reference around the phase-locked loop (50 k
pullup)
MR
LVCMOS Input
‘0' resets the internal dividers forcing Q outputs LOW. Asynchronous to the clock (50 k
pullup)
VCCA
Power Supply
PLL power supply
VCC
Power Supply
Digital power supply
GNDA
Power Supply
PLL ground
GND
Power Supply
Digital ground
Qa1
Qa0
VCC
VCC_PLL
Man_Override
VCC
Inp0bad
Inp1bad
Clk_Selected
GND
Ext_FB
V
CC
Qb
0
Qb
0
Qb
1
Qb
1
Qb
2
Qb
2
V
CC
MR
Alarm_Rese
t
CLK0
Sel_Clk
CLK1
GND
25
26
27
28
29
30
31
32
15
14
13
12
11
10
9
12
3
4
5
6
78
24
23
22
21
20
19
18
17
16
MPC9993
PLL_EN
Ext_FB
GND
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