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| 型号： | MPD800261F1-523-HN2 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 150 MHz, RISC MICROCONTROLLER, PBGA304 |
| 封装： | 19 X 19 MM, LEAD FREE, PLASTIC, FBGA-304 |
| 文件页数： | 1/45页 |
| 文件大小： | 369K |
| 代理商： | MPD800261F1-523-HN2 |
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Document No. A17989EE1V0DS00
Data Published: May 2006
ERTEC 200
Enhanced Real-Time Ethernet Controller
with 32-bit RISC CPU Core
The information in this document is subject to change without notice. Before using this document, please confirm that
this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative
for availability and additional information.
NEC Electronics Corporation 2006
PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
PD800261
DESCRIPTION
ERTEC 200 is a powerful communication block for development of PROFINET IO devices. ERTEC
200 contains a 32-bit RISC processor, an external memory interface with SDRAM and SRAM control-
ler, an LBU interface, a 2-channel real-time Ethernet interface with integrated PHYs, synchronous and
asynchronous serial ports, and general purpose I/Os. Its robust construction, specific automation func-
tions, and openness to the IT world are distinguishing features. The ERTEC 200 is housed in a 304-pin
plastic FBGA package (19 mm
× 19 mm).
Detailed functions are described in the following user’s manual. Be sure to read this manual
when you design your systems.
Preliminary User’s Manual ERTEC 200
: A17988EE1V0UM00
ARM946E-S core with max. 150 MHz
- 8 kBytes of instruction cache
- 4 kBytes of data cache
- 4 kBytes of D-TCM
- Memory protection unit
- On-chip debug and trace functionality via
JTAG interface
- ETM9 embedded trace macrocell
- Interrupt controller for 16 IRQs and 8 FIQs
Internal Multilayer AHB bus running at 50 MHz
External memory interface (EMIF) supports up
to 128 MBytes of SDRAM and up to 64 MBytes
for static memories and I/O with 4 chip selects
Single-channel DMA controller for high-speed
memory-to-memory transfers and for serial
interface support
Integrated PLL to generate internal clocks for
ARM946E-S, AHB, APB and IRT switch
Predefined Boot ROM content supporting
different download sources
Local bus unit (LBU) with 16-bit data bus to
connect external host with access to internal
ERTEC 200 resources
IRT switch block with 2 Ethernet ports
(10/100 Mbps) supporting RT and IRT traffic
- integrated Ethernet PHYs
- autonegotiation, broadcast filter
- 64 kBytes internal communication SRAM
one UART (16550 like) and one SPI interface
two 32-bit timers with prescaler, one 16-bit
timer, one 32-bit F-timer and two watchdog
timers
Max. 45 GPIOs, partly usable as interrupts
- Max. 32 GPIOs, if LBU interface is used
Various configuration options selectable during
reset
1.5 V (logic) and 3.3 V (I/O) power supply
Temperature range: TA = -40 to 85°C
Compact 304-pin plastic FBGA package
ORDERING INFORMATION
Remark:
Products with -A at the end of the part number are lead-free products.
Device
Part Number
Package
ERTEC 200
PD800261F1-523-HN2
P-FBGA304, 19
× 19 mm
PD800261F1-523-HN2-A
FEATURES
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