参数资料
型号: MRF89XA-I/MQ
厂商: Microchip Technology
文件页数: 26/140页
文件大小: 0K
描述: TXRX ISM SUB-GHZ ULP 32QFN
标准包装: 73
系列: *
频率: 863MHz ~ 870MHz,902MHz ~ 928MHz,950MHz ~ 960MHz
数据传输率 - 最大: 200kbps
调制或协议: FSK,OOK
应用: ISM
功率 - 输出: 12.5dBm
灵敏度: -113dBm
电源电压: 2.1 V ~ 3.6 V
电流 - 接收: 3mA
电流 - 传输: 25mA
数据接口: PCB,表面贴装
天线连接器: PCB,表面贴装
工作温度: -40°C ~ 85°C
封装/外壳: 32-WFQFN 裸露焊盘
包装: 托盘
MRF89XA
2.12
FIFO and Shift Register (SR)
2.13
MRF89XA Configuration, Control
In Buffered and Packet modes of operation, data to be
transmitted and data that has been received are stored
in a configurable First In First Out (FIFO) buffer. The
FIFO is accessed through the SPI data interface and
provides several interrupts for transfer management.
The FIFO is 1 byte (8 bits) wide; therefore, it only
performs byte (parallel) operations, whereas the
demodulator functions serially. A shift register (SR) is
therefore employed to interface the demodulator and
the FIFO. In Transmit mode it takes bytes from the
FIFO and outputs them serially (MSB first) at the
programmed bit rate to the modulator. Similarly, in
Receive mode the shift register gets bit-by-bit data from
the demodulator and writes them byte-by-byte to the
FIFO. This is illustrated in Figure 2-16 .
and Status Registers
The memory in the MRF89XA transceiver is
implemented as static RAM and is accessible through
the SPI port. The memory configuration of the
MRF89XA is illustrated in Figure 2-17 and Figure 2-18 .
FIGURE 2-16:
Data TX/RX
FIFO AND SHIFT
REGISTER
Byte 1
Byte 0
8
FIFO
SR (8 bits)
1
MSB
FIGURE 2-17:
0x00
LSB
MRF89XA MEMORY SPACE
0x00
0x1F
Control Registers
Data TX/RX
1
0x40
MSB
Transmit/Receive
FIFO
SHIFT REGISTER
(8 bits)
64 bytes
DS70622C-page 26
Preliminary
? 2010–2011 Microchip Technology Inc.
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