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参数资料
| 型号： | MSC1201-xx |
| 厂商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 60-Bit VFD Tube Driver with Digital Dimming and PWM Conversion Function |
| 中文描述： | 60位变频与数码管和PWM调光转换功能驱动程序 |
| 文件页数： | 11/20页 |
| 文件大小： | 135K |
| 代理商： | MSC1201-XX |
Semiconductor
MSC1201-xx
11/20
FUNCTIONAL DESCRIPTION
Power-On-Reset
The status of the internal circuit after power-on reset is as follows;
1) Shift registers and latches are reset.
2) PWM conversion mode is selected.
DATA Input
Data input is available only when the high level is applied to the "CS" pin. Input data is shifted
into shift registers through "Data" pin at the rising edge of the shift clock. The data is
automatically loaded to latches at the falling edge of "CS" signal. When M0 = "0", input data
should include display data (total of 64 bits data should be input.) and when M0 = "1", input data
should exclude display data (Total of 16-bit data shoul
d be input.)
[Data Format]
1) Display Data Input Mode
Input Data
VF Display Data
Mode Select Data
: 64 bits
: 60 bits
: 4 bits
2) Segment outputs/Shift Registers Bit Correspondence Table
The content of the table depends on a PLA code.
This table is modeled on the general purpose code of -01.
Segment output positions can be changed dependent on the PLA code, but the segment-bit
correspondence cannot be changed.
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
Bit
SEGn
GRID1
GRID2
64
D59
63
D58
62
D57
53
D48
52
M3
51
M2
50
M1
49
M0
48
D47
3
D2
2
D1
1
D0
Display
Data
Mode
Data
Display
Data
Bit
First In
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