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参数资料
| 型号： | MSC23837A-xxBS18 |
| 厂商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 8,388,608-Word x 36-Bit DRAM MODULE : FAST PAGE MODE TYPE |
| 中文描述： | 8388608字× 36位DRAM模块：快速页面模式型 |
| 文件页数： | 8/8页 |
| 文件大小： | 72K |
| 代理商： | MSC23837A-XXBS18 |
MSC23837A-xxBS18/DS18
Semiconductor
222
Notes:
1. A start-up delay of 200
μ
s is required after power-up followed by a minimum of
eight initialization cycles (
RAS
-only refresh or
CAS
before
RAS
refresh) before
proper device operation is achieved.
When using the internal refresh counter, a minimum of eight
CAS
before
RAS
initialization cycles is required.
2. AC mesurement assume t
T
= 5 ns.
3. V
IH
(Min.) and V
IL
(Max.) are reference levels for measuring input timing signals.
Transition times are measured between V
IH
and V
IL
.
4. Measured with a load circuit equivalent to 2 TTL loads and 100 pF.
5. Operation within the t
RCD
(Max.) limit ensures that t
RAC
(Max.) can be met. t
RCD
(Max.) is specified as a reference point only. If t
RCD
is greater than the specified t
RCD
(Max.) limit, access time is controlled by t
CAC
.
6. Operation within the t
RAD
(Max.) limit ensures that t
RAC
(Max.) can be met. t
RAD
(Max.) is specified as a reference point only. If t
RAD
is greater than the specified t
RAD
(Max.) limit, access time is controlled by t
AA
.
7. t
OFF
(Max.) and t
OEZ
(Max.) define the time at which the output achieves an open
circuit condition and are not referenced to output voltage levels.
8. t
RCH
or t
RRH
must be satisfied for a read cycle.
9. t
WCS
, t
CWD
, t
RWD
, t
AWD
and t
CPWD
are not restrictive operating parameters. They
are included in the data sheet as electrical characteristics only. If t
WCS
≥
t
WCS
(Min.)
the cycle is an early write cycle and the data output pin will remain in a high
impedance state throughout the entire cycle. If t
CWD
≥
t
CWD
(Min.), t
RWD
≥
t
RWD
(Min.), t
AWD
≥
t
AWD
(Min.) and t
CPWD
≥
t
CPWD
(Min.), the cycle is a read modify
write cycle and the data output pin will contain data read from the selected cell. If
neither conditions is satisfied, the data output logic state (at access time) is
undefined.
10. These parameters are referenced to
CAS
leading edge in an early write cycle and to
WE
leading edge in an
OE
control write cycle or a read modify write cycle.
11. The test mode is initiated by performing a
WE
and
CAS
before
RAS
refresh cycle.
This mode is latched and remains in effect until the exit cycle is generated.
The test mode specified in this data sheet is a 4-bit parallel test function. CA0 and CA1
are not used. In a read cycle, if all internal bits are equal, the DQ pin will indicate a high
level. If any internal bits are not equal, the DQ pin will indicate a low level. The test
mode is cleared and the memory device returned to its normal operating state by
performing a
RAS
-only refresh cycle or a
CAS
before
RAS
refresh cycle.
The 8M
￥
36 module can be tested as a 2M
￥
36 module in this test mode.
12. In a test mode read cycle, the access time parameters are delayed by 5 ns. The test
mode parameters are obtained by adding 5 ns to the normal read cycle values.
See ADDENDUM E for AC Timing Waveforms
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MSC23837A-XXDS18 | 制造商:OKI 制造商全称:OKI electronic componets 功能描述:8,388,608-Word x 36-Bit DRAM MODULE : FAST PAGE MODE TYPE |
| MSC23837D | 制造商:OKI 制造商全称:OKI electronic componets 功能描述:8,388,608-word x 36-bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE |
| MSC23837D-60BS18 | 制造商:OKI 制造商全称:OKI electronic componets 功能描述:8,388,608-word x 36-bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE |
| MSC23837D-60DS18 | 制造商:OKI 制造商全称:OKI electronic componets 功能描述:8,388,608-word x 36-bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE |
| MSC23837D-70BS18 | 制造商:OKI 制造商全称:OKI electronic componets 功能描述:8,388,608-word x 36-bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE |
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