参数资料
型号: MSC23CV23257A-xxBS4
厂商: OKI SEMICONDUCTOR CO., LTD.
英文描述: 2,097,152-Word x 32-Bit DRAM MODULE : FAST PAGE MODE TYPE WITH EDO
中文描述: 2097152字× 32位DRAM模块:快速页面模式型与江户
文件页数: 9/10页
文件大小: 64K
代理商: MSC23CV23257A-XXBS4
MSC23CV23257A-xxBS4
Semiconductor
323
See ADDENDUM I for AC Timing Waveforms
Notes:
1. A start-up delay of 200
μ
s is required after power-up, followed by a minimum of eight
initialization cycles (
RAS
-only refresh or
CAS
before
RAS
refresh) before proper device
operation is achieved.
2. The AC characteristics assume t
T
= 5 ns.
3. V
IH
(Min.) and V
IL
(Max.) are reference levels for measuring input timing signals.
Transition times (t
T
) are measured between V
IH
and V
IL
.
4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF.
5. Operation within the t
RCD
(Max.) limit ensures that t
RAC
(Max.) can be met.
t
RCD
(Max.) is specified as a reference point only. If t
RCD
is greater than the specified
t
RCD
(Max.) limit, access time is controlled by t
CAC
.
6. Operation within the t
RAD
(Max.) limit ensures that t
RAC
(Max.) can be met.
t
RAD
(Max.) is specified as a reference point only. If t
RAD
is greater than the specified
t
RAD
(Max.) limit, access time is controlled by t
AA
.
7. t
CEZ
(Max.), t
REZ
(Max.) and t
WEZ
(Max.) define the time at which the output achieves
the open circuit condition and are not referenced to output voltage levels.
8. t
CEZ
and t
REZ
must be satisfied for open circuit condition.
9. t
RCH
or t
RRH
must be satisfied for a read cycle.
10. The test mode is initiated by performing a
WE
and
CAS
before
RAS
refresh cycle.
This mode is latched and remains in effect until the exit cycle is generated.
The test mode specified in this data sheet is a 2-bit parallel test function. CA9 is not
used. In a read cycle, if all internal bits are equal, the DQ pin will indicate a high
level. If any internal bits are not equal, the DQ pin will indicate a low level.
The test mode is cleared and the memory device returned to its normal operating
state by performing a
RAS
-only refresh cycle or a
CAS
before
RAS
refresh cycle.
11. In a test mode read cycle, the value of access time parameters is delayed for 5 ns for the
specified value. These parameters should be specified in test mode cycle by adding the above
value to the specified value in this data sheet.
相关PDF资料
PDF描述
MSC23CV23257A LED GRN/O WHT/DIFF 2.0X5.0MM REC
MSC23CV43257A-xxBS8 4,194,304-Word x 32-Bit DRAM MODULE : FAST PAGE MODE TYPE WITH EDO
MSC23CV43257A 4,194,304-Word x 32-Bit DRAM MODULE : FAST PAGE MODE TYPE WITH EDO
MSC23S4641E 4,194,304 Word x 64 Bit SYNCHRONOUS DYNAMIC RAM MODULE (2BANK):
MSC23S4721E 4,194,304 Word x 72 Bit SYNCHRONOUS DYNAMIC RAM MODULE (2BANK):
相关代理商/技术参数
参数描述
MSC23CV23257D 制造商:OKI 制造商全称:OKI electronic componets 功能描述:2,097,152-word x 32-bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE WITH EDO
MSC23CV23257D-60BS4 制造商:OKI 制造商全称:OKI electronic componets 功能描述:2,097,152-word x 32-bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE WITH EDO
MSC23CV23257D-70BS4 制造商:OKI 制造商全称:OKI electronic componets 功能描述:2,097,152-word x 32-bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE WITH EDO
MSC23CV23257D-XXBS4 制造商:OKI 制造商全称:OKI electronic componets 功能描述:2,097,152-word x 32-bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE WITH EDO
MSC23CV23268D 制造商:OKI 制造商全称:OKI electronic componets 功能描述:2,097,152-word x 32-bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE WITH EDO