参数资料
型号: MSC7112VM800
厂商: Freescale Semiconductor
文件页数: 16/56页
文件大小: 0K
描述: IC DSP PROCESSOR 16BIT 400MAPBGA
标准包装: 90
系列: StarCore
类型: SC1400 内核
接口: 主机接口,I²C,UART
时钟速率: 200MHz
非易失内存: 外部
芯片上RAM: 208kB
电压 - 输入/输出: 3.30V
电压 - 核心: 1.20V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 400-LFBGA
供应商设备封装: 400-MAPBGA(17x17)
包装: 托盘
Specifications
MSC7112 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Freescale Semiconductor
23
2.5.3.1
Power-On Reset (PORESET) Pin
Asserting PORESET initiates the power-on reset flow. PORESET must be asserted externally for at least 16 CLKIN cycles after
external power to the MSC7112 reaches at least 2/3 VDD.
2.5.3.2
Reset Configuration
The MSC7112 has two mechanisms for writing the reset configuration:
From a host through the host interface (HDI16)
From memory through the I2C interface
Five signal levels (see Chapter 1 for signal description details) are sampled on PORESET deassertion to define the boot and
operating conditions:
BM[0–1]
SWTE
H8BIT
HDSP
2.5.3.3
Reset Timing Tables
Table 17 and Figure 4 describe the reset timing for a reset configuration write.
Table 16. Reset Actions for Each Reset Source
Reset Action/Reset Source
Power-On Reset
(PORESET)
Hard Reset
(HRESET)
Soft Reset
(SRESET)
External only
External or
Internal (Software
Watchdog or Bus
Monitor)
JTAG Command:
EXTEST, CLAMP,
or HIGHZ
Configuration pins sampled (refer to Section 2.5.3.1 for
details).
Yes
No
PLL and clock synthesis states Reset
Yes
No
HRESET Driven
Yes
No
Software watchdog and bus time-out monitor registers
Yes
Clock synthesis modules (STOPCTRL, HLTREQ, and
HLTACK) reset
Yes
Extended core reset
Yes
Peripheral modules reset
Yes
Table 17. Timing for a Reset Configuration Write
No.
Characteristics
Expression
Unit
1
Required external PORESET duration minimum
16/FCLKIN
clocks
2
Delay from PORESET deassertion to HRESET deassertion
521/FCLKIN
clocks
Note:
Timings are not tested, but are guaranteed by design.
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